Invention Grant
- Patent Title: Epitaxial source region for uniform threshold voltage of vertical transistors in 3D memory devices
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Application No.: US14867351Application Date: 2015-09-28
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Publication No.: US09911748B2Publication Date: 2018-03-06
- Inventor: Masatoshi Nishikawa , Kiyohiko Sakakibara , Hiroyuki Ogawa , Shuji Minagawa
- Applicant: SANDISK TECHNOLOGIES INC.
- Applicant Address: US TX Plano
- Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee Address: US TX Plano
- Agency: The Marbury Law Group PLLC
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L27/11582 ; H01L27/11556 ; H01L29/08 ; H01L29/417 ; H01L29/16 ; H01L29/04 ; H01L29/788 ; H01L21/02 ; H01L21/265 ; H01L29/66 ; H01L27/1157

Abstract:
An alternating stack of insulating layers and sacrificial material layers are formed over a substrate. Memory stack structures are formed through the alternating stack. A backside trench is formed and the sacrificial material layers are replaced with electrically conductive layers. After formation of an insulating spacer in the trench, an epitaxial pedestal structure is grown from a semiconductor portion underlying the backside trench. A source region is formed by introducing dopants into the epitaxial pedestal structure and an underlying semiconductor portion during and/or after epitaxial growth. Alternatively, the backside trench can be formed concurrently with formation of memory openings. An epitaxial pedestal structure can be formed concurrently with formation of epitaxial channel portions at the bottom of each memory opening. After formation and subsequent removal of a dummy trench fill structure in the backside trench, a source region is formed by introducing dopants into the epitaxial pedestal structure.
Public/Granted literature
- US20170092654A1 EPITAXIAL SOURCE REGION FOR UNIFORM THRESHOLD VOLTAGE OF VERTICAL TRANSISTORS IN 3D MEMORY DEVICES Public/Granted day:2017-03-30
Information query
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