Invention Grant
- Patent Title: Semiconductor device and method of making wafer level chip scale package
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Application No.: US14449914Application Date: 2014-08-01
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Publication No.: US09673093B2Publication Date: 2017-06-06
- Inventor: Ming-Che Hsieh , Chien Chen Lee , Baw-Ching Perng
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/768 ; H01L23/498 ; H01L23/525 ; H01L23/532 ; H01L21/56 ; H01L23/14 ; H01L23/31 ; H01L23/00

Abstract:
A semiconductor device has a semiconductor wafer and a first conductive layer formed over the semiconductor wafer as contact pads. A first insulating layer formed over the first conductive layer. A second conductive layer including an interconnect site is formed over the first conductive layer and first insulating layer. The second conductive layer is formed as a redistribution layer. A second insulating layer is formed over the second conductive layer. An opening is formed in the second insulating layer over the interconnect site. The opening extends to the first insulating layer in an area adjacent to the interconnect site. Alternatively, the opening extends partially through the second insulating layer in an area adjacent to the interconnect site. An interconnect structure is formed within the opening over the interconnect site and over a side surface of the second conductive layer. The semiconductor wafer is singulated into individual semiconductor die.
Public/Granted literature
- US20150041985A1 Semiconductor Device and Method of Making Wafer Level Chip Scale Package Public/Granted day:2015-02-12
Information query
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