Invention Grant
US09536964B2 Method for forming via profile of interconnect structure of semiconductor device structure
有权
用于形成半导体器件结构的互连结构的通孔轮廓的方法
- Patent Title: Method for forming via profile of interconnect structure of semiconductor device structure
- Patent Title (中): 用于形成半导体器件结构的互连结构的通孔轮廓的方法
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Application No.: US14725002Application Date: 2015-05-29
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Publication No.: US09536964B2Publication Date: 2017-01-03
- Inventor: Wei-Yin Shiao , Che-Cheng Chang , Tai-Shin Cheng , Wei-Ting Chen
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L29/41
- IPC: H01L29/41 ; H01L29/417 ; H01L29/66 ; H01L21/768

Abstract:
A method for forming the semiconductor device structure is provided. The method includes forming a first metal layer over a substrate and forming a dielectric layer over the first metal layer. The method includes forming an antireflection layer over the dielectric layer, forming a hard mask layer over the antireflection layer and forming a patterned photoresist layer over the hard mask layer. The method includes etching a portion of the antireflection layer by performing a first etching process and etching through the antireflection layer and etching a portion of the dielectric layer by performing a second etching process. The method includes etching through the dielectric layer by performing a third etching process to form a via portion on the first metal layer. The via portion includes a first sidewall and a second sidewall, and the slope of the first sidewall is different from that of the second sidewall.
Public/Granted literature
- US20160351669A1 METHOD FOR FORMING VIA PROFILE OF INTERCONNECT STRUCTURE OF SEMICONDUCTOR DEVICE STRUCTURE Public/Granted day:2016-12-01
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