Invention Grant
- Patent Title: Self-alignment structure for wafer level chip scale package
- Patent Title (中): 晶圆级芯片尺寸封装的自对准结构
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Application No.: US13940626Application Date: 2013-07-12
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Publication No.: US09048149B2Publication Date: 2015-06-02
- Inventor: Yu-Chia Lai , Hsien-Ming Tu , Tung-Liang Shao , Hsien-Wei Chen , Chang-Pin Huang , Ching-Jung Yang
- Applicant: Taiwan Semiconductor Manufacturing Co., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agent Maschoff Brennan
- Main IPC: H01L23/00
- IPC: H01L23/00

Abstract:
A packaged semiconductor device includes a semiconductor substrate, a metal pad, a metal base, a polymer insulating layer, a copper-containing structure and a conductive bump. The metal pad and the metal base are disposed on the semiconductor substrate. The polymer insulating layer overlies the metal base and the semiconductor substrate. The copper-containing structure is disposed over the polymer insulating layer, and includes a support structure and a post-passivation interconnect (PPI) line. The support structure is aligned with the metal base. The PPI line is located partially within the support structure, and extends out through an opening of the support structure, in which a top of the support structure is elevated higher than a top of the PPI line. The conductive bump is held by the support structure.
Public/Granted literature
- US20150014846A1 Self-alignment Structure for Wafer Level Chip Scale Package Public/Granted day:2015-01-15
Information query
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