Invention Grant
US08989246B2 Method and circuit of clock and data recovery with built in jitter tolerance test
有权
时钟和数据恢复的方法和电路，内置抖动容限测试
- Patent Title: Method and circuit of clock and data recovery with built in jitter tolerance test
- Patent Title (中): 时钟和数据恢复的方法和电路，内置抖动容限测试
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Application No.: US14041828Application Date: 2013-09-30
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Publication No.: US08989246B2Publication Date: 2015-03-24
- Inventor: Pei-Si Wu
- Applicant: Realtek Semiconductor Corp.
- Applicant Address: TW Hsinchu
- Assignee: Realtek Semiconductor Corp.
- Current Assignee: Realtek Semiconductor Corp.
- Current Assignee Address: TW Hsinchu
- Agency: Muncy, Geissler, Olds & Lowe, P.C.
- Priority: TW100105396A 20110218
- Main IPC: H04B3/46
- IPC: H04B3/46 ; H04B17/00 ; H04Q1/20 ; H04L1/20 ; H03L7/08 ; H03L7/081 ; H03L7/093
Abstract:
A clock and data recovery circuit with built in jitter tolerance test is disclosed. Imposing jitter on a filter inside a CDR loop to cause phase disturbances to the clock and data recovery circuit, thereby to test the jitter tolerance of the clock and data recovery circuit. Accordingly, IC test cost is significantly reduced by increasing few circuit sizes.
Public/Granted literature
- US20140029657A1 METHOD AND CIRCUIT OF CLOCK AND DATA RECOVERY WITH BUILT IN JITTER TOLERANCE TEST Public/Granted day:2014-01-30
Information query
