A method and apparatus to design a circuit is described. In on embodiment, the method comprises selecting a target clock for a design of the circuit, and determining a plurality of latencies for a portion of the circuit. The method further comprises determining a representation of a data flow graph for the portion of the circuit, the data flow graph having a first node connected with a second node by a number of extra delays determined based on the target clock and the plurality of latencies, the first node and second node representing paths that start from and end in registers in the portion of the circuit, the first node connecting to a node between a first input of the portion of the circuit and an input of a register of the portion of the circuit. The method continues to retime the design for the circuit to operate at the target clock based on the representation of the data flow graph, wherein at least one of the selecting, determining, and retiming is performed by a processor.