Invention Grant
US08829940B2 Method for testing a partially assembled multi-die device, integrated circuit die and multi-die device
有权
用于测试部分组装的多芯片器件,集成电路管芯和多管芯器件的方法
- Patent Title: Method for testing a partially assembled multi-die device, integrated circuit die and multi-die device
- Patent Title (中): 用于测试部分组装的多芯片器件,集成电路管芯和多管芯器件的方法
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Application No.: US13120793Application Date: 2009-09-26
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Publication No.: US08829940B2Publication Date: 2014-09-09
- Inventor: Fransciscus Geradus Marie de Jong , Alexander Sebastian Biewenga
- Applicant: Fransciscus Geradus Marie de Jong , Alexander Sebastian Biewenga
- Applicant Address: NL Eindhoven
- Assignee: NXP, B.V.
- Current Assignee: NXP, B.V.
- Current Assignee Address: NL Eindhoven
- Priority: EP08165280 20080926
- International Application: PCT/IB2009/054219 WO 20090926
- International Announcement: WO2010/035238 WO 20100401
- Main IPC: G01R31/02
- IPC: G01R31/02 ; G01R31/26 ; G01R31/3185 ; G01R31/317 ; G01R31/319 ; G01R31/28 ; G01R31/3183 ; G01R19/00

Abstract:
The present invention discloses a method of testing a partially assembled multi-die device (1) by providing a carrier (300) comprising a device-level test data input (12) and a device-level test data output (18); placing a first die on the carrier, the first die having a test access port (100c) comprising a primary test data input (142), a secondary test data input (144) and a test data output (152), the test access port being controlled by a test access port controller (110); communicatively coupling the secondary test data input (144) of the first die to the device-level test data input (12), and the test data output (152) of the first die to the device-level test data output (18); providing the first die with configuration information to bring the first die in a state in which the first die accepts test instructions from its secondary test data input (144); testing the first die, said testing including providing the secondary test data input (144) of the first die with test instructions through the device-level test data input (12); and collecting a test result for the first die on the device-level test data output (18). Consequently, a die of a partially assembled multi-die device such as a System-in-Package may be tested using its integrated boundary scan test architecture.
Public/Granted literature
- US20120126846A1 METHOD FOR TESTING A PARTIALLY ASSEMBLED MULTI-DIE DEVICE, INTEGRATED CIRCUIT DIE AND MULTI-DIE DEVICE Public/Granted day:2012-05-24
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