Invention Grant
- Patent Title: Reduced latency memory column redundancy repair
- Patent Title (中): 减少延迟内存列冗余修复
-
Application No.: US13270653Application Date: 2011-10-11
-
Publication No.: US08693262B2Publication Date: 2014-04-08
- Inventor: Steven C. Sullivan
- Applicant: Steven C. Sullivan
- Applicant Address: US CA Cupertino
- Assignee: Apple Inc.
- Current Assignee: Apple Inc.
- Current Assignee Address: US CA Cupertino
- Agency: Meyertons, Hood, Kivlin, Kowert & Goetzel. P.C.
- Agent Stephen J. Curran
- Main IPC: G11C7/00
- IPC: G11C7/00

Abstract:
A memory column redundancy mechanism includes a memory having a number of data output ports each configured to output one data bit of a data element. The memory also includes a number of memory columns each connected to a corresponding respective data port. Each memory column includes a plurality of bit cells that are coupled to a corresponding sense amplifier that may differentially output a respective data bit from the plurality of bit cells on an output signal and a complemented output signal. The memory further includes an output selection unit that may select as the output data bit for a given data output port, one of the output signal of the sense amplifier associated with the given data output port or the complemented output signal of the sense amplifier associated with an adjacent data output port dependent upon a respective shift signal for each memory column.
Public/Granted literature
- US20130091329A1 REDUCED LATENCY MEMORY COLUMN REDUNDANCY REPAIR Public/Granted day:2013-04-11
Information query