Invention Grant
- Patent Title: Using entropy in an colony optimization circuit design from high level synthesis
- Patent Title (中): 在高级综合的殖民地优化电路设计中使用熵
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Application No.: US13658760Application Date: 2012-10-23
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Publication No.: US08645882B2Publication Date: 2014-02-04
- Inventor: Mustafa Ispir , Levent Oktem
- Applicant: Synopsys, Inc.
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Agent Judith A. Szepesi
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A method for designing an integrated circuit is described. The method comprises converting behavioral descriptions of the integrated circuit to register transfer level (RTL) descriptions. The method comprises at least one of the behavioral descriptions including frame synthesis with an input frame and a corresponding output frame. In one embodiment, the method further comprises providing at least two solutions for performing partial and complete operations for simulations as hardware component combinations, associating each solution with a cost, and selecting the solution with the lowest cost as the hardware component combination for a final design of the integrated circuit.
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