A clock signal generator having first and second coarse delay circuits connected in series delays pulses of a reference signal having period TP to produce pulses of the clock signal. The first coarse delay circuit delays pulses of the reference signal with a delay resolution of TP/N seconds over a range spanning TP seconds to produce pulses of an output signal. The second coarse delay circuit delays pulses of the output signal of the first coarse delay circuit over a range spanning TP seconds with a delay resolution of TP/M seconds to provide pulses of the clock signal with a timing resolution of TP/(M*N) seconds when the integers N and M are relatively prime.