Invention Grant
- Patent Title: Split charge storage node outer spacer process
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Application No.: US11924169Application Date: 2007-10-25
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Publication No.: US07883963B2Publication Date: 2011-02-08
- Inventor: Minghao Shen , Chungho Lee , Hiroyuki Kinoshita , Huaqiang Wu
- Applicant: Minghao Shen , Chungho Lee , Hiroyuki Kinoshita , Huaqiang Wu
- Applicant Address: US CA Sunnyvale
- Assignee: Spansion LLC
- Current Assignee: Spansion LLC
- Current Assignee Address: US CA Sunnyvale
- Agency: Turocy & Watson, LLP
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
Memory cells containing two split sub-lithographic charge storage nodes on a semiconductor substrate and methods for making the memory cells are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing an exposed portion of a fist poly layer between sloping side surfaces or outer surfaces of spacers while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing an exposed portion of a charge storage layer between sloping side surfaces or outer surfaces of spacers, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.
Public/Granted literature
- US20090108330A1 SPLIT CHARGE STORAGE NODE OUTER SPACER PROCESS Public/Granted day:2009-04-30
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