Invention Grant
US07768287B2 Methods and apparatus for managing defective processors through power gating
有权
通过电源门控管理有缺陷的处理器的方法和设备
- Patent Title: Methods and apparatus for managing defective processors through power gating
- Patent Title (中): 通过电源门控管理有缺陷的处理器的方法和设备
-
Application No.: US11620873Application Date: 2007-01-08
-
Publication No.: US07768287B2Publication Date: 2010-08-03
- Inventor: Atsushi Hayashi , Akiyuki Hatakeyama , Taichi Niki , Yoichi Nishino
- Applicant: Atsushi Hayashi , Akiyuki Hatakeyama , Taichi Niki , Yoichi Nishino
- Applicant Address: JP Tokyo
- Assignee: Sony Computer Enterainment Inc.
- Current Assignee: Sony Computer Enterainment Inc.
- Current Assignee Address: JP Tokyo
- Agency: Gibson & Dernier LLP
- Agent Matthew B. Dernier, Esq.
- Main IPC: G01R31/02
- IPC: G01R31/02 ; G06F1/26
Abstract:
Methods and apparatus provide for: selectively supplying a first source of power to a plurality of circuit blocks of a system using a plurality of gate circuits responsive to respective control signals provided by at least one control circuit; and providing a second source of power to operate the control circuit before the first source of power is available to the gate circuits such that the control signals are valid before such availability.
Public/Granted literature
- US20070176625A1 Methods And Apparatus For Managing Defective Processors Through Power Gating Public/Granted day:2007-08-02
Information query
