Invention Grant
US07673206B2 Method and system for routing scan chains in an array of processor resources
失效
用于在处理器资源阵列中路由扫描链的方法和系统
- Patent Title: Method and system for routing scan chains in an array of processor resources
- Patent Title (中): 用于在处理器资源阵列中路由扫描链的方法和系统
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Application No.: US11901184Application Date: 2007-09-14
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Publication No.: US07673206B2Publication Date: 2010-03-02
- Inventor: Richard Conlin
- Applicant: Richard Conlin
- Applicant Address: US MA Westborough
- Assignee: Tilera Corporation
- Current Assignee: Tilera Corporation
- Current Assignee Address: US MA Westborough
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
The present invention provides a method and system for routing a group of scan chains to a group of processor resources in a semiconductor chip. The group of processor resources is arranged in rows or columns. The group of processor resources in each row or column is connected through a plurality of scan chains. The first processor resource in each row or column is connected to input scan-chain pins, and the last processor resource in each row or column is connected to output scan-chain pins. A test-pattern generator, generating test signals, sends the test signals to the group of processor resources by using the group of scan chains within the semiconductor chip. The responses of the processor resources corresponding to the test signals are analyzed to detect and locate any error in the manufacture of the semiconductor chip.
Public/Granted literature
- US20090077437A1 Method and system for routing scan chains in an array of processor resources Public/Granted day:2009-03-19
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