Invention Grant
- Patent Title: Process for erasing chalcogenide variable resistance memory bits
- Patent Title (中): 擦除硫族化物可变电阻记忆位的过程
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Application No.: US11745209Application Date: 2007-05-07
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Publication No.: US07643333B2Publication Date: 2010-01-05
- Inventor: Jon Daley
- Applicant: Jon Daley
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dickstein Shapiro LLP
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C5/06

Abstract:
A method of erasing a chalcogenide variable resistance memory cell is provided. The chalcogenide variable resistance memory cell includes a p-doped substrate with an n-well and a chalcogenide variable resistance memory element. The method includes the step of applying to the variable resistance memory element a voltage that is less than a fixed voltage of the substrate. The applied voltage induces an erase current to flow from the p-doped substrate through the n-well and through the variable resistance memory element.
Public/Granted literature
- US20080310208A1 PROCESS FOR ERASING CHALCOGENIDE VARIABLE RESISTANCE MEMORY BITS Public/Granted day:2008-12-18
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