Invention Grant
- Patent Title: Error correction code system with augmented detection features
-
Application No.: US17343136Application Date: 2021-06-09
-
Publication No.: US11750226B2Publication Date: 2023-09-05
- Inventor: Eric Masson , Nagaraju Balasubramanya
- Applicant: NVIDIA CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA CORPORATION
- Current Assignee: NVIDIA CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Artegis Law Group, LLP
- Main IPC: H03M13/29
- IPC: H03M13/29 ; G06F11/10

Abstract:
Various embodiments include an error correction code (ECC) system that provides protection against various errors in addition to data bit errors. In general, ECC codes protect against data bit errors, where one or more data bits in a data word contain the wrong value. The ECC code is based on the original data bits, such that a data bit error results in a data word that is inconsistent with the ECC code generated for and stored with the data word. The present embodiments generate ECC codes based on address information and/or sequencing information in addition to the data bits in the data word. As a result, the present embodiments detect bit errors in this address information and/or sequencing information. Such errors include write address decoding errors, read address decoding errors, write enable errors, and stale data errors.
Public/Granted literature
- US20220399905A1 ERROR CORRECTION CODE SYSTEM WITH AUGMENTED DETECTION FEATURES Public/Granted day:2022-12-15
Information query
IPC分类: