- Patent Title: Semiconductor device and method of forming low voltage power MOSFETs using graphene for metal layers and graphene nanoribbons for channel and drain enhancement regions of power vertical and lateral MOSFETs
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Application No.: US17075753Application Date: 2020-10-21
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Publication No.: US11545565B2Publication Date: 2023-01-03
- Inventor: Samuel J. Anderson
- Applicant: IceMos Technology Limited
- Applicant Address: GB Belfast
- Assignee: IceMos Technology Limited
- Current Assignee: IceMos Technology Limited
- Current Assignee Address: GB Belfast
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L29/76 ; H01L29/16 ; H01L21/02 ; H01L29/66

Abstract:
A semiconductor device has a substrate and graphene with semiconducting properties or diamond region formed on the substrate. The graphene with semiconducting properties or diamond region is formed on or within the substrate using liquid-phase-epitaxy growth of graphene enabled by a catalytic alloy of Ni and Cu. The substrate can be silicon, silicon carbide, gallium arsenide, gallium nitride, germanium, or indium phosphide. A semiconductor component is formed over the graphene with semiconducting properties or diamond region and substrate. The semiconductor component can be a power MOSFET, IGBT, or CTIGBT with a gate structure formed over the substrate, source region adjacent to the gate structure, and drain region adjacent to the gate structure opposite the source region. The graphene with semiconducting properties or diamond region is formed under a gate of the MOSFET to reduce drain to source resistance, as well as providing radiation hardening for the device.
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