Invention Grant
- Patent Title: Multi-mode low-precision inner-product computation circuits for massively parallel neural inference engine
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Application No.: US16653366Application Date: 2019-10-15
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Publication No.: US11270196B2Publication Date: 2022-03-08
- Inventor: Jun Sawada , Filipp A. Akopyan , Rathinakumar Appuswamy , John V. Arthur , Andrew S. Cassidy , Pallab Datta , Steven K. Esser , Myron D. Flickner , Dharmendra S. Modha , Tapan K. Nayak , Carlos O. Otero
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Foley Hoag, LLP
- Agent Erik A. Huestis; Stephen J. Kenny
- Main IPC: G06N3/063
- IPC: G06N3/063 ; G06N3/04

Abstract:
Neural inference chips for computing neural activations are provided. In various embodiments, the neural inference chip is adapted to: receive an input activation tensor comprising a plurality of input activations; receive a weight tensor comprising a plurality of weights; Booth recode each of the plurality of weights into a plurality of Booth-coded weights, each Booth coded value having an order; multiply the input activation tensor by the Booth coded weights, yielding a plurality of results for each input activation, each of the plurality of results corresponding to the orders of the Booth-coded weights; for each order of the Booth-coded weights, sum the corresponding results, yielding a plurality of partial sums, one for each order; and compute a neural activation from a sum of the plurality of partial sums.
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