A frequency doubler includes a multiplexer, a digitally controlled delay circuit, a divide-by-two circuit, a duty cycle detector, and a controller. The multiplexer receives a first clock and output a second clock in accordance with a third clock, in which the first clock has a fifty percent duty cycle and is a two-phase clock having a first phase and a second phase. The digitally controlled delay circuit receives the second clock and outputs a fourth clock in accordance with a digital word. The divide-by-two circuit receives the fourth clock and outputs the third clock. The duty cycle detector receives the second clock and outputs a logical signal in accordance with a comparison of a duty cycle of the second clock with a target duty cycle value. The controller outputs the digital word in accordance with the logical signal.