Invention Grant
- Patent Title: Semiconductor device with stacked die device
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Application No.: US16401587Application Date: 2019-05-02
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Publication No.: US10910345B2Publication Date: 2021-02-02
- Inventor: Chiang-Lin Shih , Pei-Jhen Wu , Ching-Hung Chang , Hsih-Yang Chiu
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW New Taipei
- Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee Address: TW New Taipei
- Agency: Muncy, Geissler, Olds & Lowe, P.C.
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L25/065 ; H01L23/528 ; H01L23/00 ; H01L23/498

Abstract:
The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first die, a second die, a first redistribution layer, a second redistribution layer, a first interconnect structure, and a second interconnect structure. The second die is stacked on the first die, the first redistribution layer is disposed between a first substrate of the first die and a second ILD layer of the second die, and the second redistribution layer is disposed on a second substrate of the second die. The first interconnect structure connects the first redistribution layer to one of first metal lines of the first die, and the second interconnect structure connects the second redistribution layer to one of the second metal lines in the second ILD layer.
Public/Granted literature
- US20200350284A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2020-11-05
Information query
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