Invention Grant
- Patent Title: System and method for correcting non-ideal wafer topography
-
Application No.: US15941568Application Date: 2018-03-30
-
Publication No.: US10770327B2Publication Date: 2020-09-08
- Inventor: Cheng-Mu Lin , Chi-Hung Liao , Yi-Ming Dai , Yueh Lin Yang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Main IPC: H01L21/68
- IPC: H01L21/68 ; H04N5/225 ; G06T7/00 ; H01L21/67
Abstract:
A scanner includes a light source configured to apply a light to a backside of a wafer. The light is reflected from the backside of the wafer. A first mirror is configured to receive the light from the backside of the wafer and reflect the light. A sensor is configured to receive the light from the first mirror and generate an output signal indicative of a backside topography of the wafer.
Public/Granted literature
- US20190035664A1 SYSTEM AND METHOD FOR CORRECTING NON-IDEAL WAFER TOPOGRAPHY Public/Granted day:2019-01-31
Information query
IPC分类:
