Invention Grant
- Patent Title: Effective junction formation in vertical transistor structures by engineered bottom source/drain epitaxy
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Application No.: US16369990Application Date: 2019-03-29
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Publication No.: US10763343B2Publication Date: 2020-09-01
- Inventor: Alexander Reznicek , Shogo Mochizuki
- Applicant: International Business Machines Corporation
- Applicant Address: CA Ottawa
- Assignee: ELPIS TECHNOLOGIES INC.
- Current Assignee: ELPIS TECHNOLOGIES INC.
- Current Assignee Address: CA Ottawa
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/78 ; H01L29/08 ; H01L29/161 ; H01L29/167 ; H01L29/49 ; H01L21/768 ; H01L21/225 ; H01L21/02 ; H01L21/28 ; H01L23/535 ; H01L29/165

Abstract:
A vertical transistor structure is provided that includes a bottom source/drain structure that includes a doped semiconductor buffer layer that contains a first dopant species having a first diffusion rate, and an epitaxial doped semiconductor layer that contains a second dopant species that has a second diffusion rate that is less than the first diffusion rate. During a junction anneal, the first dopant species readily diffuses from the doped semiconductor buffer layer into a pillar portion of a base semiconductor substrate to provide the bottom source/drain extension and bottom source/drain junction. No diffusion overrun is observed. During the junction anneal, the second dopant species remains in the epitaxial doped semiconductor layer providing a low resistance contact. The second dopant species does not interfere with the bottom source/drain extension and bottom source/drain junction due to limited diffusion of the second dopant species.
Public/Granted literature
- US20190229205A1 EFFECTIVE JUNCTION FORMATION IN VERTICAL TRANSISTOR STRUCTURES BY ENGINEERED BOTTOM SOURCE/DRAIN EPITAXY Public/Granted day:2019-07-25
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