公开(公告)号：US10937883B2

公开(公告)日：2021-03-02

申请号：US16662907

申请日：2019-10-24

Applicant: ELPIS TECHNOLOGIES INC.

Inventor： Choonghyun Lee ,  Takashi Ando ,  Jingyun Zhang ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/08 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/3215 ,  H01L23/535 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12 ,  H01L27/088 ,  H01L29/417

Abstract: Vertical transport field effect transistors (FETs) having improved device performance are provided. Notably, vertical transport FETs having a gradient threshold voltage are provided. The gradient threshold voltage is provided by introducing a threshold voltage modifying dopant into a physically exposed portion of a metal gate layer composed of an n-type workfunction TiN. The threshold voltage modifying dopant changes the threshold voltage of the original metal gate layer.

公开(公告)号：US10790199B2

公开(公告)日：2020-09-29

申请号：US16371621

申请日：2019-04-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Choonghyun Lee ,  Richard G. Southwick

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/10 ,  H01L29/78 ,  H01L27/092 ,  H01L21/02 ,  H01L21/311 ,  H01L21/324 ,  H01L29/161

Abstract: A method of forming fin structures that includes providing at least one silicon germanium containing fin structure, and forming a fin liner on the at least one silicon germanium containing fin structure. The fin liner includes a silicon germanium and oxygen containing layer. The method continues with annealing the at least on silicon germanium containing fin structure having the fin liner present thereon. During the annealing, the silicon germanium oxygen containing layer reacts with the silicon germanium containing fin structure to provide surface formation of a silicon rich layer on the silicon germanium containing fin structure.

公开(公告)号：US10755949B2

公开(公告)日：2020-08-25

申请号：US16016920

申请日：2018-06-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam ,  Robert R. Robison

IPC: H01L23/62 ,  H01L21/324 ,  H01L29/866 ,  H01L27/02 ,  H01L29/861

Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an cathode on a substrate and a anode on the substrate. The anode is in electrical contact with the cathode. The method further includes forming a device between the cathode and the anode. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

公开(公告)号：US10727299B2

公开(公告)日：2020-07-28

申请号：US16149598

申请日：2018-10-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kevin K. Chan ,  Pouya Hashemi ,  Tak H. Ning ,  Alexander Reznicek

IPC: H01L29/08 ,  H01L29/735 ,  H01L23/31 ,  H01L29/161 ,  H01L29/20 ,  H01L29/10 ,  H01L29/737 ,  H01L29/165 ,  H01L29/04 ,  H01L29/06 ,  H01L23/29 ,  H01L29/66 ,  H01L21/683 ,  H01L21/02 ,  H01L21/308 ,  H01L21/265 ,  H01L21/74

Abstract: A lateral bipolar junction transistor (LBJT) device that may include a dielectric stack including a pedestal of a base region passivating dielectric and a nucleation dielectric layer; and a base region composed of a germanium containing material or a type III-V semiconductor material in contact with the pedestal of the base region passivating dielectric. An emitter region and collector region may be present on opposing sides of the base region contacting a sidewall of the pedestal of the base region passivating dielectric and an upper surface of the nucleation dielectric layer.

公开(公告)号：US10727139B2

公开(公告)日：2020-07-28

申请号：US16240146

申请日：2019-01-04

Applicant: ELPIS TECHNOLOGIES INC.

Inventor： Terry Hook ,  Ardasheir Rahman ,  Joshua Rubin ,  Chen Zhang

IPC: H01L21/84 ,  H01L27/12 ,  H01L23/00 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L27/06 ,  H01L21/8234 ,  H01L21/822 ,  H01L27/088

Abstract: Techniques facilitating three-dimensional monolithic vertical field effect transistor logic gates are provided. A logic device can comprise a first vertical transport field effect transistor formed over and adjacent a substrate and a first bonding film deposited over the first vertical transport field effect transistor. The logic device can also comprise a second vertical transport field effect transistor comprising a second bonding film and stacked on the first vertical transport field effect transistor. The second bonding film can affix the second vertical transport field effect transistor to the first vertical transport field effect transistor. In addition, the logic device can comprise one or more monolithic inter-layer vias that extend from first respective portions of the second vertical transport field effect transistor to second respective portions of the first vertical transport field effect transistor and through the first bonding film and the second bonding film.

公开(公告)号：US10727121B2

公开(公告)日：2020-07-28

申请号：US16201448

申请日：2018-11-27

Applicant: ELPIS TECHNOLOGIES INC.

Inventor： Robert L. Bruce ,  Cyril Cabral, Jr. ,  Gregory M. Fritz ,  Eric A. Joseph ,  Michael F. Lofaro ,  Hiroyuki Miyazoe ,  Kenneth P. Rodbell ,  Ghavam Shahidi

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: The present disclosure relates to integrated circuits and to methods of manufacturing interconnects of integrated circuits. For example, an integrated circuit includes a surface of the integrated circuit and an interconnect formed on the surface and comprising a metal. An average grain size of the metal of the interconnect is greater than or equal to at least half of a line width of the interconnect. In another example, a method for manufacturing an interconnect of an integrated circuit includes depositing a layer of a metal onto a surface of the integrated circuit, annealing the metal, patterning a first hard mask for placement over the metal and forming a line of the interconnect and a first via of the interconnect by performing a timed etch of the metal using the first hard mask.

公开(公告)号：US10714341B2

公开(公告)日：2020-07-14

申请号：US15591584

申请日：2017-05-10

Applicant: ELPIS TECHNOLOGIES INC.

Inventor： Guy M. Cohen ,  Sebastian U. Engelmann ,  Steve Holmes ,  Jyotica V. Patel

IPC: H01L21/02 ,  H01L21/027 ,  G03F7/20 ,  H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L23/528

Abstract: Lift-off methods for fabricating metal line patterns on a substrate are provided. For example, a method to fabricate a device includes forming a sacrificial layer on a substrate and forming a photoresist mask over the sacrificial layer, isotropically etching a portion of the sacrificial layer exposed through an opening of the photoresist mask to form an undercut region in the sacrificial layer below the photoresist mask, wherein the undercut region defines an overhang structure, and anisotropically etching a portion of the sacrificial layer exposed through the opening of the photoresist mask to form an opening through the sacrificial layer down to the substrate. Metallic material is deposited to cover the photoresist mask and to at least partially fill the opening formed in the sacrificial layer without coating the overhang structure with metallic material. The sacrificial layer is dissolved to lift-off the metallic material covering the photoresist mask.

公开(公告)号：US10692722B2

公开(公告)日：2020-06-23

申请号：US16235309

申请日：2018-12-28

Applicant: International Business Machines Corporation

Inventor： Praneet Adusumilli ,  Alexander Reznicek ,  Oscar van der Straten ,  Chih-Chao Yang

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L21/285 ,  H01L29/78 ,  H01L23/532 ,  H01L21/768 ,  H01L29/51 ,  H01L29/165 ,  H01L23/485

Abstract: After forming a contact opening in a dielectric material layer located over a substrate, a metal liner layer comprising a nitride of an alloy and a metal contact layer comprising the alloy that provides the metal liner layer are deposited in-situ in the contact opening by sputter deposition in a single process and without an air break. Compositions of the metal liner layer and the metal contact layer can be changed by varying gas compositions employed in the sputtering process.

公开(公告)号：US11063129B2

公开(公告)日：2021-07-13

申请号：US16521777

申请日：2019-07-25

Applicant: ELPIS TECHNOLOGIES INC.

Inventor： Kangguo Cheng ,  Choonghyun Lee ,  Juntao Li ,  Peng Xu

IPC: H01L29/417 ,  H01L29/66 ,  H01L21/762 ,  H01L21/324 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/10

Abstract: Provided is a method for forming a semiconductor structure. In embodiments of the invention, the method includes laterally forming a spacer on a side of the semiconductor structure. The method further includes performing a thermal anneal on the semiconductor structure. The method further includes performing an etch to remove materials formed by the thermal anneal.

公开(公告)号：US10978576B2

公开(公告)日：2021-04-13

申请号：US16597713

申请日：2019-10-09

Applicant: ELPIS TECHNOLOGIES INC.

Inventor： Chi-Chun Liu ,  Chun Wing Yeung ,  Robin Hsin Kuo Chao ,  Zhenxing Bi ,  Kristin Schmidt ,  Yann Mignot

IPC: H01L29/66 ,  H01L21/311 ,  H01L29/40 ,  H01L29/423 ,  H01L21/3105 ,  H01L29/78

Abstract: Techniques for VFET gate length control are provided. In one aspect, a method of forming a VFET device includes: patterning fins in a substrate; forming first polymer spacers alongside opposite sidewalls of the fins; forming second polymer spacers offset from the fins by the first polymer spacers; removing the first polymer spacers selective to the second polymer spacers; reflowing the second polymer spacers to close a gap to the fins; forming a cladding layer above the second polymer spacers; removing the second polymer spacers; forming gates along opposite sidewalls of the fins exposed in between the bottom spacers and the cladding layer, wherein the gates have a gate length Lg set by removal of the second polymer spacers; forming top spacers above the cladding layer; and forming top source and drains above the top spacers. A VFET device is also provided.