Invention Grant
- Patent Title: Heterogeneous SoC IP core placement in an interconnect to optimize latency and interconnect performance
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Application No.: US14925904Application Date: 2015-10-28
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Publication No.: US10554496B2Publication Date: 2020-02-04
- Inventor: Eric Norige , Sailesh Kumar
- Applicant: NetSpeed Systems
- Applicant Address: US CA San Jose
- Assignee: NetSpeed Systems
- Current Assignee: NetSpeed Systems
- Current Assignee Address: US CA San Jose
- Agency: Spectrum IP Law Group LLC
- Main IPC: H04L12/24
- IPC: H04L12/24 ; H04L12/721

Abstract:
Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the position of hosts of various size and shape in a NoC topology based on the connectivity, bandwidth and latency requirements of the system traffic flows and certain performance optimization metrics such as system interconnect latency and interconnect cost. The example embodiments selects hosts for relocation consideration and determines a new possible position for them in the NoC based on the system traffic specification, shape and size of the hosts and by using probabilistic function to decide if the relocation is carried out or not. The procedure is repeated over new sets of hosts until certain optimization targets are satisfied or repetition count is exceeded.
Public/Granted literature
- US20170063634A1 HETEROGENEOUS SOC IP CORE PLACEMENT IN AN INTERCONNECT TO OPTIMIZE LATENCY AND INTERCONNECT PERFORMANCE Public/Granted day:2017-03-02
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