Invention Grant
- Patent Title: Chip package and chip packaging method
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Application No.: US15950302Application Date: 2018-04-11
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Publication No.: US10541186B2Publication Date: 2020-01-21
- Inventor: Zhiqi Wang , Guoliang Xie , Hanqing Hu
- Applicant: China Wafer Level CSP Co., Ltd.
- Applicant Address: CN Suzhou, Jiangsu
- Assignee: China Wafer Level CSP Co., Ltd.
- Current Assignee: China Wafer Level CSP Co., Ltd.
- Current Assignee Address: CN Suzhou, Jiangsu
- Agency: Wolf, Greenfield & Sacks, P.C.
- Priority: CN201710448280 20170614; CN201720692113U 20170614
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/31 ; H01L27/146 ; H01L21/56 ; H01L21/78 ; H01L21/683 ; H01L21/768
Abstract:
A chip package and a chip packaging method are provided. The package includes: a chip to be packaged, a reinforcing layer and solder bumps. The chip to be packaged includes a first surface and a second surface opposite to each other, the first surface includes a sensing region and first contact pads, and the first contact pads are electrically coupled to the sensing region. The reinforcing layer covers the first surface of the chip to be packaged. The solder bumps are provided on the second surface of the chip to be packaged. The solder bump is electrically connected to the first contact pad and is configured to electrically connect with an external circuit.
Public/Granted literature
- US20180366387A1 CHIP PACKAGE AND CHIP PACKAGING METHOD Public/Granted day:2018-12-20
Information query
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