Invention Grant
- Patent Title: Molded substrate package in fan-out wafer level package
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Application No.: US15858103Application Date: 2017-12-29
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Publication No.: US10403580B2Publication Date: 2019-09-03
- Inventor: Lizabeth Keser , Thomas Ort , Thomas Wagner , Bernd Waidhas
- Applicant: Intel IP Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel IP Corporation
- Current Assignee: Intel IP Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L23/00 ; H01L21/48 ; H01L23/31 ; H01L23/498 ; H01L21/56
Abstract:
An electronic device may include a semiconductor die. The electronic device may include a first routing layer. The first routing layer may be coupled to the semiconductor die. A first plurality of routing traces may be in electrical communication with the semiconductor die. The first plurality of routing traces may be positioned within a first routing footprint. The first routing footprint may have a width greater than a width of the semiconductor die.A second routing layer may be coupled to the first routing layer. A second plurality of routing traces may be in electrical communication with the first plurality of routing traces. The second plurality of routing traces may be positioned within a second routing footprint. The second routing footprint may have a width greater than the width of the first routing footprint.
Public/Granted literature
- US20190206800A1 MOLDED SUBSTRATE PACKAGE IN FAN-OUT WAFER LEVEL PACKAGE Public/Granted day:2019-07-04
Information query
IPC分类:
