Invention Grant
- Patent Title: Laminated interposers and packages with embedded trace interconnects
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Application No.: US15187739Application Date: 2016-06-20
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Publication No.: US10283492B2Publication Date: 2019-05-07
- Inventor: Nader Gamini
- Applicant: Invensas Corporation
- Applicant Address: US CA San Jose
- Assignee: Invensas Corporation
- Current Assignee: Invensas Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: H01L25/18
- IPC: H01L25/18 ; H01L21/48 ; H01L23/498 ; H01L25/065 ; H01L23/552 ; H01L25/10 ; H01L25/00 ; H01L23/66 ; H01L23/36 ; H05K1/03 ; H05K1/18 ; H01L25/16

Abstract:
Laminated interposers and packages, with embedded trace interconnects are provided. An example process for making an interposer or package achieves vertical conductive vias in the package by depositing conductive traces on multiple wafers or panes, then laminating these substrates into a stack, thereby embedding the conductive traces. The laminated stack is sliced to dimensions of an interposer or electronic package. A side of the sliced stack is then used as the top of the interposer or package, rendering some of the horizontally laid traces into vertical conductive vias. The interposer or package can be finished or developed by adding redistribution layers on the top and bottom surfaces, and active and passive components. Electronic components can also be embedded in the laminated stack. Some of the stack layers can be active dies, such as memory controllers, memory storage arrays, and processors, to form a memory subsystem or self-contained computing device.
Public/Granted literature
- US20160379967A1 LAMINATED INTERPOSERS AND PACKAGES WITH EMBEDDED TRACE INTERCONNECTS Public/Granted day:2016-12-29
Information query
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