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公开(公告)号：US11209850B2
公开(公告)日：2021-12-28
申请号：US16790920
申请日：2020-02-14
Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
Inventor： Yao-Wei Yang
Abstract: A termination voltage regulation apparatus with transient response enhancement includes a termination voltage regulator and a transient response enhancer. The termination voltage regulator provides a termination voltage at a termination voltage terminal, including first and second switching units. The transient response enhancer, coupled to the termination voltage regulator, is utilized for enhancing transient response of the termination voltage regulator, including a first enhancement circuit for sensing a first signal associated with the first switching unit and enabling a first control terminal of the first switching unit to be at a first voltage in response to the first signal in a sinking mode; and a second enhancement circuit for sensing a second signal associated with the second switching unit and enabling a second control terminal of the second switching unit to be at a second voltage in response to the second signal in a sourcing mode.
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公开(公告)号：US10958259B2
公开(公告)日：2021-03-23
申请号：US16837634
申请日：2020-04-01
Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
Inventor： Szu-Chun Tsao , Yang-Jing Huang , Ya-Mien Hsu
IPC: H03K7/08
Abstract: A pulse width modulation output stage incorporates a half bridge output stage, a gate control circuit, a detection circuit, and a control logic. The half bridge output stage has a first transistor and a second transistor connected in series between a power supply node and a ground node. The gate control circuit outputs a pulse width modulation signal to drive the first transistor and the second transistor. The detection circuit detects whether or not a glitch occurs in one of the gate voltages of the first and second transistor so as to generate a control code. The logic circuit varies the delay time of the pulse width modulation signal based on the control code.
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公开(公告)号：US20210049095A1
公开(公告)日：2021-02-18
申请号：US16539041
申请日：2019-08-13
Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
Inventor： PEI-JEY HUANG , TSE-HUA YAO
Abstract: The present application proposes a memory chip includes a plurality of memory banks, a plurality of address pins, and a pseudo-address determining circuit. The plurality of address pins is arranged for receiving a plurality of address signals corresponding to the plurality of memory banks, respectively. The pseudo-address determining circuit has a plurality of input terminals coupled to the plurality of address pins, respectively, and a plurality of output terminals coupled to the plurality of memory banks. The pseudo-address determining circuit generates a pseudo-address table for the plurality of memory banks when the memory chip is powered-up. The pseudo-address table has a plurality of pseudo-addresses corresponding to the plurality of memory banks, respectively. The present application also provides a memory module that incorporates the memory chip and a method for pseudo-accessing memory banks of the memory chip.
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公开(公告)号：US10916293B1
公开(公告)日：2021-02-09
申请号：US16747553
申请日：2020-01-21
Applicant: Elite Semiconductor Memory Technology Inc.
Inventor： Ya-Chun Lai , Po-Hsun Wu , Jen-Shou Hsu
IPC: G11C11/40 , G11C11/406 , G11C7/06 , G06F12/02 , G11C11/409
Abstract: A target row refresh method includes: providing first table having M entries each capable of storing information of target row address; providing second table having K entries respectively capable of storing information of different/identical candidate row addresses; determining whether an input address in an input address register matches address information recorded in the first table; when not match, determining whether to update information of a target row latch by using the input address in the input address register according to a sample policy so as to determine whether to compare the input address with address information recorded in the second table to determine a target row address; and performing a target row refresh operation to refresh a memory device's row(s) adjacent to a target row corresponding to the target row address.
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公开(公告)号：US10771017B2
公开(公告)日：2020-09-08
申请号：US16242011
申请日：2019-01-08
Applicant: Elite Semiconductor Memory Technology Inc.
Inventor： Shao-Ming Sun
Abstract: An amplifier circuit with novel design is provided. The amplifier circuit includes an input stage, a resistor, an output stage, an intermediate stage and a gm circuit. The input stage is coupled to a first supply voltage, and is arranged to receive an input voltage and a feedback current. The resistor is coupled between the input voltage and the input stage. The output stage is coupled to a second supply voltage, and is arranged to provide an output voltage for driving a load. The intermediate stage is coupled between the input stage and the output stage, and includes a level shifter. The gm circuit is coupled to the input stage, and is arranged to compare the input voltage with a common mode voltage, and thereby generates a compensate current for the input stage.
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Patent Agency Ranking
公开(公告)号：US10587196B1
公开(公告)日：2020-03-10
申请号：US16282352
申请日：2019-02-22
Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
Inventor： I-Hsiu Ho
Abstract: A constant on-time controller has a voltage divider, a current ripple extractor, a one-shot on-timer, a comparator and a flip flop. The voltage divider generates a feedback voltage according to a regulator output voltage. The current ripple extractor senses a current in an energy storage inductor of a buck regulator flowing through flowing through an output capacitor's ESR, and generates an extracted ripple current having no DC component accordingly. The one-shot on-timer outputs a constant-on time control signal according to a buck regulator input voltage and the regulator output voltage. The modulation circuit outputs a modulation signal according to a reference voltage signal, the feedback voltage and the extracted ripple current. The flip flop generates a control signal to the buck regulator according to the modulation signal and the constant-on time control signal. An off-time of the buck regulator is determined according to the modulation signal.
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公开(公告)号：US20190259461A1
公开(公告)日：2019-08-22
申请号：US15902325
申请日：2018-02-22
Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
Inventor： Chih-Hao CHEN
Abstract: An erasing method used in a flash memory comprising at least one memory block divided into a plurality of memory sectors is illustrated. Whether the memory block or the memory sector corresponding to an address has at least one under-erased transistor memory cell according to a sector enable signal is verified, wherein the sector enable signal is determined according to whether the memory block has at least one over-erased transistor memory cell. The transistor memory cells of the memory block or the memory sector will be erased according to the sector enable signal if the memory block or the memory sector corresponding to the address that has the under-erased transistor memory cell.
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8.发明授权公开(公告)号：US10014848B1
公开(公告)日：2018-07-03
申请号：US15687115
申请日：2017-08-25
Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
Inventor： I-Hsiu Ho
IPC: H03K5/003 , H03K19/0185
CPC classification number: H03K5/003 , H03F3/45475 , H03F3/45618 , H03F2203/45538 , H03F2203/45588 , H03K19/018521
Abstract: A compensation circuit for compensating an input voltage offset of an error amplifier has a level shifter, a first trimming circuit, a second trimming circuit, and a compensation current sinking device. The level shifter shifts levels of a feedback voltage and a predetermined reference voltage and outputs a level shifted feedback voltage and a level shifted reference voltage. The first trimming circuit adjusts the level shifted reference voltage by trimming a first resistance thereof according to a trimming code, wherein the trimming code has the ratio relation of the input voltage offset and a resistance to be trimmed. The second trimming circuit adjusts the level shifted feedback voltage by trimming a second resistance thereof according to a trimming code. The compensation current sinking device sinks currents passing through the first and second trimming circuits.
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公开(公告)号：US10008930B1
公开(公告)日：2018-06-26
申请号：US15806307
申请日：2017-11-07
Applicant: Elite Semiconductor Memory Technology Inc.
Inventor： Yao-Wei Yang
Abstract: A bootstrap circuit applied to a first transistor of a direct-current (DC) to DC converter includes a second transistor, a bootstrapping capacitor and a clamping circuit, wherein the bootstrapping capacitor has a first terminal and a second terminal, and the first terminal is coupled to a source terminal of a transistor, and the source terminal of the second transistor is coupled to the first transistor; and the clamping circuit is coupled between a gate terminal of the second transistor and the second terminal of the bootstrapping capacitor, and is arranged to maintain a voltage drop between the second terminal of the bootstrapping capacitor and the gate terminal of the second transistor. A drain terminal of the second transistor is coupled to a first reference voltage, and a maximum of a voltage level of the gate terminal of the first transistor is greater than the first reference voltage.
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公开(公告)号：US09997230B1
公开(公告)日：2018-06-12
申请号：US15628203
申请日：2017-06-20
Applicant: Elite Semiconductor Memory Technology Inc.
Inventor： Min-Chung Chou
IPC: H03K17/00 , H03K19/003 , H03K17/16 , H01H47/00 , H03K17/06 , H01L27/12 , G11C11/4074 , G05F3/24 , H03K5/24 , G05F1/46 , H03H19/00 , G11C5/14
CPC classification number: G11C11/4074 , G05F1/46 , G05F1/465 , G05F3/24 , G11C5/147 , G11C7/02 , H01H47/00 , H01L27/12 , H03H19/004 , H03K3/013 , H03K5/24 , H03K5/2472 , H03K17/302
Abstract: Embodiments of the invention relate to a reference voltage pre-processing circuit and method for a reference voltage buffer. The embodiments include a filter to control/reduce the noise and/or interference attached to a reference voltage to be provided to a reference voltage buffer by passing the reference voltage via two transistor in series. Furthermore, the embodiments include an auxiliary voltage circuit which interfaces the filter and the reference voltage buffer to avoid that the reference voltage buffer get an invalid reference voltage.
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