公开(公告)号：US08835232B2

公开(公告)日：2014-09-16

申请号：US13606694

申请日：2012-09-07

Applicant: Hemanth Jagannathan ,  Sivananda K. Kanakasabapathy

Inventor： Hemanth Jagannathan ,  Sivananda K. Kanakasabapathy

IPC: H01L29/78

CPC classification number: H01L27/1203 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/42384 ,  H01L29/4908

Abstract: A disposable dielectric structure is formed on a semiconductor-on-insulator (SOI) substrate such that all physically exposed surfaces of the disposable dielectric structure are dielectric surfaces. A semiconductor material is selectively deposited on semiconductor surfaces, while deposition of any semiconductor material on dielectric surfaces is suppressed. After formation of at least one gate spacer and source and drain regions, a planarization dielectric layer is deposited and planarized to physically expose a top surface of the disposable dielectric structure. The disposable dielectric structure is replaced with a replacement gate stack including a gate dielectric and a gate conductor portion. Lower external resistance can be provided without impacting the short channel performance of a field effect transistor device.

Abstract translation: 在绝缘体上半导体（SOI）基板上形成一次性介质结构，使得一次性介质结构的所有物理暴露表面都是电介质表面。 半导体材料选择性地沉积在半导体表面上，同时抑制任何半导体材料在电介质表面上的沉积。 在形成至少一个栅极间隔物和源极和漏极区域之后，平坦化介电层被沉积并平坦化以物理暴露一次性介电结构的顶表面。 一次性介质结构被包括栅极电介质和栅极导体部分的替换栅极堆叠替代。 可以提供较低的外部电阻，而不会影响场效应晶体管器件的短沟道性能。

公开(公告)号：US20140024209A1

公开(公告)日：2014-01-23

申请号：US13552035

申请日：2012-07-18

Applicant: Ryan O. Jung ,  Sivananda K. Kanakasabapathy

Inventor： Ryan O. Jung ,  Sivananda K. Kanakasabapathy

IPC: H01L21/28

CPC classification number: H01L21/28132 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/32139 ,  H01L21/76224 ,  H01L21/823456 ,  H01L29/66575 ,  H01L29/78

Abstract: A method of forming multiple different width dimension features simultaneously. The method includes forming multiple sidewall spacers of different widths formed from different combinations of conformal layers on different mandrels, removing the mandrels, and simultaneously transferring the pattern of the different sidewall spacers into an underlying layer.

Abstract translation: 同时形成多个不同宽度尺寸特征的方法。 该方法包括形成由不同心轴上的适形层的不同组合形成的不同宽度的多个侧壁间隔物，去除心轴，以及同时将不同侧壁间隔物的图案转移到下面的层中。

公开(公告)号：US20140023834A1

公开(公告)日：2014-01-23

申请号：US13571496

申请日：2012-08-10

Applicant: Ryan O. Jung ,  Sivananda K. Kanakasabapathy ,  Yunpeng Yin

Inventor： Ryan O. Jung ,  Sivananda K. Kanakasabapathy ,  Yunpeng Yin

IPC: B32B3/10

CPC classification number: H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  Y10T428/24802

Abstract: At least one mask layer formed over a substrate includes at least one of a dielectric material and a metallic material. By forming a first pattern in one of the at least one mask layer, a patterned mask layer including said first pattern is formed. An overlying structure including a second pattern that includes at least one blocking area is formed over said patterned mask layer. Portions of said patterned mask layer that do not underlie said blocking area are removed. The remaining portions of the patterned mask layer include a composite pattern that is an intersection of the first pattern and the second pattern. The patterned mask layer includes a dielectric material or a metallic material, and thus, enables high fidelity pattern transfer into an underlying material layer.

Abstract translation: 在衬底上形成的至少一个掩模层包括电介质材料和金属材料中的至少一种。 通过在所述至少一个掩模层之一中形成第一图案，形成包括所述第一图案的图案化掩模层。 在所述图案化掩模层上形成包括包括至少一个阻挡区域的第二图案的覆盖结构。 除去不在所述阻挡区域下面的所述图案化掩模层的部分被去除。 图案化掩模层的其余部分包括作为第一图案和第二图案的交叉的复合图案。 图案化掩模层包括电介质材料或金属材料，因此能够将高保真图案转移到下面的材料层中。

公开(公告)号：US08614486B2

公开(公告)日：2013-12-24

申请号：US13605260

申请日：2012-09-06

Applicant: Balasubramanian S. Haran ,  Hemanth Jagannathan ,  Sivananda K. Kanakasabapathy ,  Sanjay Mehta

Inventor： Balasubramanian S. Haran ,  Hemanth Jagannathan ,  Sivananda K. Kanakasabapathy ,  Sanjay Mehta

IPC: H01L29/02 ,  H01L21/02

CPC classification number: H01L29/66772 ,  H01L29/6653 ,  H01L29/78621

Abstract: A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions.

Abstract translation: 在通过各向异性蚀刻共形介电层形成第一栅极间隔物之后对栅极电介质进行构图，以最小化过蚀刻到半导体层中。 在一个实施例中，执行选择性外延以顺序地形成凸起的外延半导体部分，一次性栅极间隔物和升高的源极和漏极区域。 去除一次性栅极间隔物，并将离子注入进行到隆起的外延半导体部分的暴露部分中以形成源极和漏极延伸区域。 在另一个实施例中，用于源极和漏极延伸形成的离子注入在形成第一栅极间隔物的各向异性蚀刻之前通过保形介电层进行。 升高的外延半导体部分或构象介电层的存在防止了源极和漏极延伸区域中的半导体材料的完全非晶化，从而使结晶源极和漏极延伸区域再生长。

公开(公告)号：US08420464B2

公开(公告)日：2013-04-16

申请号：US13100589

申请日：2011-05-04

Applicant: Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Sivananda K. Kanakasabapathy ,  Hemant Adhikari

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Sivananda K. Kanakasabapathy ,  Hemant Adhikari

IPC: H01L21/8238

CPC classification number: H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211

Abstract: A method of fabricating a semiconductor device that includes at least two fin structures, wherein one of the at least two fin structures include epitaxially formed in-situ doped second source and drain regions having a facetted exterior sidewall that are present on the sidewalls of the fin structure. In another embodiment, the disclosure also provides a method of fabricating a finFET that includes forming a recess in a sidewall of a fin structure, and epitaxially forming an extension dopant region in the recess that is formed in the fin structure. Structures formed by the aforementioned methods are also described.

Abstract translation: 一种制造半导体器件的方法，其包括至少两个翅片结构，其中所述至少两个翅片结构中的一个包括外延形成的原位掺杂的第二源极和漏极区域，其具有存在于鳍的侧壁上的刻面外侧壁 结构体。 在另一个实施例中，本发明还提供一种制造finFET的方法，其包括在鳍结构的侧壁中形成凹槽，并且在形成在鳍结构中的凹槽中外延形成延伸掺杂区域。 还描述了通过上述方法形成的结构。

公开(公告)号：US20130020615A1

公开(公告)日：2013-01-24

申请号：US13188789

申请日：2011-07-22

Applicant: Su Chen Fan ,  David Horak ,  Sivananda K. Kanakasabapathy

Inventor： Su Chen Fan ,  David Horak ,  Sivananda K. Kanakasabapathy

IPC: H01L21/28 ,  H01L29/80

CPC classification number: H01L21/28 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L27/0207 ,  H01L29/78

Abstract: A method includes depositing a dummy fill material over exposed portions of a substrate and a gate stack disposed on the substrate, removing portions of the dummy fill material to expose portions of the substrate, forming a layer of spacer material over the exposed portions of the substrate, the dummy fill material and the gate stack, removing portions of the layer of spacer material to expose portions of the substrate and the dummy fill material, depositing a dielectric layer over the exposed portions of the spacer material, the substrate, and the gate stack, removing portions of the dielectric layer to expose portions of the spacer material, removing exposed portions of the spacer material to expose portions of the substrate and define at least one cavity in the dielectric layer, and depositing a conductive material in the at least one cavity.

Abstract translation: 一种方法包括在衬底的暴露部分和设置在衬底上的栅极堆叠上沉积虚拟填充材料，去除虚拟填充材料的部分以暴露衬底的部分，在衬底的暴露部分上形成间隔材料层 ，虚拟填充材料和栅极堆叠，去除间隔物材料层的部分以暴露衬底和虚拟填充材料的部分，在间隔材料，衬底和栅极堆叠的暴露部分上沉积介电层 去除所述介电层的部分以暴露所述间隔物材料的部分，去除所述间隔物材料的暴露部分以暴露所述基底的部分并且限定所述电介质层中的至少一个腔，以及在所述至少一个腔中沉积导电材料 。

公开(公告)号：US20130001749A1

公开(公告)日：2013-01-03

申请号：US13171865

申请日：2011-06-29

Applicant: JOHN C. ARNOLD ,  Sivananda K. Kanakasabapathy ,  Stefan Schmitz ,  Yunpeng Yin

Inventor： JOHN C. ARNOLD ,  Sivananda K. Kanakasabapathy ,  Stefan Schmitz ,  Yunpeng Yin

IPC: H01L29/06 ,  H01L21/311

CPC classification number: H01L21/3086 ,  H01L21/3088 ,  H01L21/845

Abstract: A method for formation of a fin field effect transistor (FinFET) device includes forming a mandrel mask and a large feature (FX) mask on a metal hardmask layer of a film stack, the film stack including a silicon on insulator (SOI) layer located underneath the metal hardmask layer; etching the mandrel mask and the FX mask simultaneously into the metal hardmask layer; and etching the mandrel mask and the FX mask into the SOI layer using the etched metal hardmask layer as a mask.

Abstract translation: 一种用于形成鳍状场效应晶体管（FinFET）器件的方法包括在膜堆叠的金属硬掩模层上形成心轴掩模和大特征（FX）掩模，所述膜堆叠包括位于绝缘体上的硅（SOI）层 在金属硬掩模层下面; 将芯棒掩模和FX掩模同时蚀刻到金属硬掩模层中; 并使用蚀刻的金属硬掩模层作为掩模将芯棒掩模和FX掩模蚀刻到SOI层中。

公开(公告)号：US20120326241A1

公开(公告)日：2012-12-27

申请号：US13603572

申请日：2012-09-05

Applicant: Balasubramanian S. Haran ,  Sivananda K. Kanakasabapathy

Inventor： Balasubramanian S. Haran ,  Sivananda K. Kanakasabapathy

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/823807 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Contact via holes are etched in a dielectric material layer overlying a semiconductor layer to expose the topmost surface of the semiconductor layer. The contact via holes are extended into the semiconductor material layer by continuing to etch the semiconductor layer so that a trench having semiconductor sidewalls is formed in the semiconductor material layer. A metal layer is deposited over the dielectric material layer and the sidewalls and bottom surface of the trench. Upon an anneal at an elevated temperature, a metal semiconductor alloy region is formed, which includes a top metal semiconductor alloy portion that includes a cavity therein and a bottom metal semiconductor alloy portion that underlies the cavity and including a horizontal portion. A metal contact via is formed within the cavity so that the top metal semiconductor alloy portion laterally surrounds a bottom portion of a bottom portion of the metal contact via.

Abstract translation: 在覆盖半导体层的电介质材料层中蚀刻接触孔，以露出半导体层的最上表面。 接触通孔延伸到半导体材料层中，继续蚀刻半导体层，使得在半导体材料层中形成具有半导体侧壁的沟槽。 在电介质材料层和沟槽的侧壁和底表面上沉积金属层。 在高温退火时，形成金属半导体合金区域，其包括顶部金属半导体合金部分，其中包括空腔，底部金属半导体合金部分位于空腔下方并包括水平部分。 金属接触通孔形成在空腔内，使得顶部金属半导体合金部分横向地围绕金属接触通孔的底部的底部。

公开(公告)号：US20120302057A1

公开(公告)日：2012-11-29

申请号：US13558441

申请日：2012-07-26

Applicant: John Christopher Arnold ,  Sean D. Burns ,  Sivananda K. Kanakasabapathy ,  Yunpeng Yin

Inventor： John Christopher Arnold ,  Sean D. Burns ,  Sivananda K. Kanakasabapathy ,  Yunpeng Yin

IPC: H01L21/768

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76897

Abstract: A method for patterning self-aligned vias in a dielectric. The method includes forming a first trench partially through a hard mask, where the trench corresponds to a desired wiring path in the dielectric. The trench should be formed on a sub-lithographic scale. Then, form a second trench, also of a sub-lithographic scale, that intersects the first trench. The intersection forms a pattern extending through the depth of the hard mask, and corresponds to a via hole in the dielectric. The via hole is etched into the dielectric through the hard mask. Then the first trench is extended through the hard mask and the exposed area is etched to form the wiring path, which intersects the via hole. Conductive material is deposited to form a sub-lithographic via and wiring. This method may be used to form multiple vias of sub-lithographic proportions and with a sub-lithographic pitch.

Abstract translation: 用于在电介质中图案化自对准通孔的方法。 该方法包括通过硬掩模部分地形成第一沟槽，其中沟槽对应于电介质中期望的布线路径。 沟槽应该在亚光刻尺上形成。 然后，形成与第一沟槽相交的第二沟槽，也是亚光刻标尺。 交叉点形成延伸穿过硬掩模的深度的图案，并且对应于电介质中的通孔。 通孔通过硬掩模蚀刻到电介质中。 然后将第一沟槽延伸穿过硬掩模，并且暴露的区域被蚀刻以形成与通孔相交的布线路径。 导电材料沉积以形成亚光刻通孔和布线。 该方法可以用于形成亚光刻比例的多个通孔和亚光刻间距。

公开(公告)号：US08164128B2

公开(公告)日：2012-04-24

申请号：US11926845

申请日：2007-10-29

Applicant: Sivananda K. Kanakasabapathy ,  Michael C. Gaidis

Inventor： Sivananda K. Kanakasabapathy ,  Michael C. Gaidis

IPC: H01L29/94

CPC classification number: H01L43/12 ,  H01L21/76897 ,  H01L27/222 ,  H01L43/08 ,  H01L2924/3011

Abstract: Techniques for forming a magnetic device are provided. In one aspect, a magnetic device includes a magnetic tunnel junction and a dielectric layer formed over at least a portion of the magnetic tunnel junction. The dielectric layer is configured to have an underlayer proximate to the magnetic tunnel junction, and an overlayer on a side of the underlayer opposite the magnetic tunnel junction. The magnetic device further includes a via hole running substantially vertically through the dielectric layer and being self-aligned with the magnetic tunnel junction.

Abstract translation: 提供了用于形成磁性装置的技术。 在一个方面，磁性装置包括形成在磁性隧道结的至少一部分上的磁性隧道结和介电层。 介电层被配置为具有靠近磁性隧道结的底层，以及与该底层的与磁性隧道结相对的一侧上的覆盖层。 磁性器件还包括通孔，该通孔基本垂直穿过介电层并与磁性隧道结自对准。