公开(公告)号：US09923045B2

公开(公告)日：2018-03-20

申请号：US13681013

申请日：2012-11-19

Applicant: Renesas Electronics Corporation

Inventor： Kenichiro Hijioka ,  Akira Tanabe ,  Yoshihiro Hayashi

IPC: H01F5/00 ,  H01F27/28 ,  H01L49/02 ,  H01F17/00 ,  H01F41/04 ,  H01F27/34

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01F27/34 ,  H01F41/041 ,  H01F2017/002 ,  H01F2017/004 ,  H01F2017/0086 ,  Y10T29/4902 ,  Y10T29/49071

Abstract: An inductor element is formed in a multiple layer lead structure including a lead, an insulative layer that insulates leads above and below, and a via provided in the insulative layer and connecting leads above and below wherein lead layers are multiply laminated layers, characterized in that: at least a portion of at least a pair of vertically adjacent leads are coiled leads; the coiled leads are connected in series, wherein current directions of vertically adjacent coiled leads are the same by a via provided on an end portion thereof, and form a serial inductance; and an inter-lead capacitance of the vertically adjacent coiled leads is larger than an inter-lead capacitance between other coiled leads formed in the same lead layer.

公开(公告)号：US09257390B2

公开(公告)日：2016-02-09

申请号：US14551505

申请日：2014-11-24

Applicant: Renesas Electronics Corporation

Inventor： Mari Amano ,  Munehiro Tada ,  Naoya Furutake ,  Yoshihiro Hayashi

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53233 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate, an insulating film formed above the semiconductor substrate, and a multilayered wiring formed in a prescribed area within the insulating film. The multilayered wiring includes a dual damascene wiring positioned on at least one layer of the multilayered wiring. The dual damascene wiring includes an alloy having copper as a principal component. A concentration of at least one metallic element contained as an added component of the alloy in a via connected to the dual damascene wiring is 10% or more higher in a via connected to a wiring whose width exceeds by five or more times a diameter of the via than that in another via connected to another wiring of a smallest width in a same upper wiring layer of the multilayered wiring.

Abstract translation: 半导体器件包括半导体衬底，形成在半导体衬底上的绝缘膜，以及形成在绝缘膜内的规定区域中的多层布线。 多层布线包括位于多层布线的至少一层上的双镶嵌布线。 双镶嵌线包括以铜为主要成分的合金。 在连接到双镶嵌布线的通孔中作为合金的添加成分含有的至少一种金属元素的浓度在连接到宽度超过五倍或更多倍的布线的通孔中为10％以上 通过连接到多层布线的同一上布线层中的最小宽度的另一布线的通孔。

公开(公告)号：US09053961B2

公开(公告)日：2015-06-09

申请号：US13680757

申请日：2012-11-19

Applicant: Renesas Electronics Corporation

Inventor： Kishou Kaneko ,  Naoya Inoue ,  Yoshihiro Hayashi

IPC: H01L27/088 ,  H01L29/66 ,  H01L27/12 ,  H01L23/522

CPC classification number: H01L27/1259 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02565 ,  H01L21/28 ,  H01L21/44 ,  H01L21/465 ,  H01L21/47635 ,  H01L23/522 ,  H01L27/088 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/1237 ,  H01L27/124 ,  H01L27/1251 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/66477 ,  H01L29/66969 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interlayer insulating film is formed. Then a first gate electrode and a second gate electrode are buried in the interlayer insulating film. Then, an anti-diffusion film is formed over the interlayer insulating film, over the first gate electrode, and over the second gate electrode. Then, a first semiconductor layer is formed over the anti-diffusion film which is present over the first gate electrode. Then, an insulating cover film is formed over the upper surface and on the lateral side of the first semiconductor layer and over the anti-diffusion film. Then, a semiconductor film is formed over the insulating cover film. Then, the semiconductor film is removed selectively to leave a portion positioned over the second gate electrode, thereby forming a second semiconductor layer.

Abstract translation: 形成层间绝缘膜。 然后将第一栅电极和第二栅电极埋入层间绝缘膜中。 然后，在层间绝缘膜上方，在第一栅电极上方和第二栅电极上形成防扩散膜。 然后，在存在于第一栅电极上的抗扩散膜上形成第一半导体层。 然后，在第一半导体层的上表面和横向侧上以及反扩散膜之上形成绝缘覆盖膜。 然后，在绝缘覆盖膜上形成半导体膜。 然后，选择性地去除半导体膜以留下位于第二栅电极上的部分，从而形成第二半导体层。

公开(公告)号：US09034740B2

公开(公告)日：2015-05-19

申请号：US13887668

申请日：2013-05-06

Applicant: Renesas Electronics Corporation

Inventor： Hironori Yamamoto ,  Fuminori Ito ,  Yoshihiro Hayashi

IPC: H01L21/33 ,  H01L21/02 ,  H01L29/02 ,  H01L21/768 ,  H01L23/532 ,  H01L27/22

CPC classification number: H01L29/0657 ,  H01B3/46 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/7682 ,  H01L21/76825 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/535 ,  H01L27/228 ,  H01L29/02 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The deposition rate of a porous insulation film is increased, and the film strength of the porous insulation film is improved. Two or more organic siloxane raw materials each having a cyclic SiO structure as a main skeleton thereof, and having mutually different structures, are vaporized, and transported with a carrier gas to a reactor (chamber), and an oxidant gas including an oxygen atom is added thereto. Thus, a porous insulation film is formed by a plasma CVD (Chemical Vapor Deposition) method or a plasma polymerization method in the reactor (chamber). In the step, the ratio of the flow rate of the added oxidant gas to the flow rate of the carrier gas is more than 0 and 0.08 or less.

Abstract translation: 多孔绝缘膜的沉积速率提高，多孔绝缘膜的膜强度提高。 两种以上的具有环状SiO结构作为主要骨架并且具有相互不同结构的有机硅氧烷原料被蒸发并用载气输送到反应器（室），并且包含氧原子的氧化剂气体是 加入。 因此，在反应器（室）中通过等离子体CVD（化学气相沉积）法或等离子体聚合法形成多孔绝缘膜。 在该步骤中，添加的氧化剂气体的流量与载气的流量的比率大于0和0.08以下。

公开(公告)号：US20130134418A1

公开(公告)日：2013-05-30

申请号：US13745291

申请日：2013-01-18

Applicant: Renesas Electronics Corporation

Inventor： Yoshihiro Hayashi ,  Naoya INOUE ,  Kishou KANEKO

IPC: H01L29/41

CPC classification number: H01L21/76807 ,  H01L21/28282 ,  H01L21/76877 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/242 ,  H01L29/41 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66757 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/792

Abstract: A semiconductor device, includes a semiconductor substrate, a first interconnect layer formed over the semiconductor substrate, a gate electrode formed in the first interconnect layer, a gate insulating film formed over the gate electrode, a second interconnect layer formed over the gate insulating film, an oxide semiconductor layer formed in the second interconnect layer, and a via formed in the second interconnect layer and connected to the oxide semiconductor layer. The gate electrode, the gate insulating film and the oxide semiconductor layer overlap in a plan view.

Abstract translation: 一种半导体器件，包括半导体衬底，形成在半导体衬底上的第一互连层，形成在第一互连层中的栅电极，形成在栅电极上的栅极绝缘膜，形成在栅极绝缘膜上的第二互连层， 形成在第二互连层中的氧化物半导体层和形成在第二互连层中并连接到氧化物半导体层的通孔。 栅电极，栅极绝缘膜和氧化物半导体层在平面图中重叠。

公开(公告)号：US09558824B2

公开(公告)日：2017-01-31

申请号：US14992724

申请日：2016-01-11

Applicant: Renesas Electronics Corporation

Inventor： Makoto Ueki ,  Takashi Hase ,  Yoshihiro Hayashi

IPC: G11C11/00 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C13/0097 ,  G11C2013/0071 ,  G11C2013/0083 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146

Abstract: To improve information retention resistance of a resistance change memory which requires high information retention resistance. On the assumption that a special data storage memory and a general-purpose data storage memory are distinguished from each other, a forming operation small in resistance rise rate is used for an information writing operation of the special data storage memory. A switching operation is used for information writing of the general-purpose data storage memory. That is, the special data storage memory is configured so as to store information while adapting an initial resistance state to “0” whereas adapting a low resistance state to “1”. On the other hand, the general-purpose data storage memory is configured so as to store information while adapting a high resistance state to “0” whereas adapting a low resistance state to “1”.

Abstract translation: 提高需要高信息保持电阻的电阻变化存储器的信息保持电阻。 假设专用数据存储器和通用数据存储器彼此区分，电阻上升速率小的形成操作被用于特殊数据存储器的信息写入操作。 切换操作用于通用数据存储存储器的信息写入。 也就是说，特殊数据存储存储器被配置为在将初始电阻状态适配为“0”的同时存储信息，而将低电阻状态适配为“1”。 另一方面，通用数据存储存储器被配置为在使高电阻状态适应“0”的同时存储信息，而使低电阻状态适应“1”。

公开(公告)号：US09349844B2

公开(公告)日：2016-05-24

申请号：US14527019

申请日：2014-10-29

Applicant: Renesas Electronics Corporation

Inventor： Naoya Inoue ,  Kishou Kaneko ,  Yoshihiro Hayashi

IPC: H01L21/336 ,  H01L29/12 ,  H01L29/78 ,  H01L29/66 ,  H01L27/12 ,  H01L23/522 ,  H01L29/423 ,  H01L23/532 ,  H01L21/768 ,  H01L29/786 ,  H01L21/02

CPC classification number: H01L29/42384 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02565 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention makes it possible to lower the on resistance of a semiconductor element without hindering the function of a diffusion prevention film in a semiconductor device having the semiconductor element that uses a wire in a wiring layer as a gate electrode and has a gate insulation film in an identical layer to the diffusion prevention film. A first wire and a gate electrode are embedded into the surface layer of an insulation layer comprising a first wiring layer. A diffusion prevention film is formed between the first wiring layer and a second wiring layer. A gate insulation film is formed by: forming a recess over the upper face of the diffusion prevention film in the region overlapping with the gate electrode and around the region; and thinning the part.

Abstract translation: 本发明可以降低半导体元件的导通电阻，而不会妨碍具有使用布线层中的导线的半导体元件作为栅电极的半导体器件中的扩散防止膜的功能，并具有栅极绝缘膜 在与扩散防止膜相同的层中。 第一导线和栅电极嵌入到包括第一布线层的绝缘层的表面层中。 在第一布线层和第二布线层之间形成扩散防止膜。 栅极绝缘膜通过以下方式形成：在与栅电极重叠的区域和区域周围形成在扩散防止膜的上表面上的凹部; 并使部件变薄。

公开(公告)号：US09257435B2

公开(公告)日：2016-02-09

申请号：US14516164

申请日：2014-10-16

Applicant: Renesas Electronics Corporation

Inventor： Kenzo Manabe ,  Naoya Inoue ,  Kenichiro Hijioka ,  Yoshihiro Hayashi

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L27/1085 ,  H01L21/768 ,  H01L23/5223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10894 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes: a multilayer wiring layer located over a substrate and in which multiple wiring layers configured by a wiring and an insulating layer are stacked; a memory circuit which is formed in a memory circuit region in the substrate and has a capacitance element embedded in a concave part located in the multilayer wiring layer; a logic circuit which is formed in a logic circuit region in the substrate; an upper part coupling wiring which is stacked over the capacitance element configured by a lower part electrode, a capacitor insulating film and an upper part electrode; and a cap layer which is formed on the upper surface of the wiring configuring the logic circuit. The upper surface of the upper part coupling wiring and the upper surface of the cap film are provided on the same plane.

Abstract translation: 一种半导体器件，包括：多层布线层，位于基板的上方，其中堆叠由布线和绝缘层构成的多个布线层; 存储电路，其形成在所述基板的存储电路区域中，并且具有嵌入在位于所述多层布线层中的凹部的电容元件; 形成在基板的逻辑电路区域中的逻辑电路; 层叠在由下部电极，电容绝缘膜和上部电极构成的电容元件上的上部耦合布线; 以及形成在构成逻辑电路的布线的上表面上的盖层。 上部连接线的上表面和盖膜的上表面设置在同一平面上。

公开(公告)号：US09236430B2

公开(公告)日：2016-01-12

申请号：US14701828

申请日：2015-05-01

Applicant: Renesas Electronics Corporation

Inventor： Hironori Yamamoto ,  Fuminori Ito ,  Yoshihiro Hayashi

IPC: H01L23/58 ,  H01L29/06 ,  H01L23/535 ,  H01B3/46

CPC classification number: H01L29/0657 ,  H01B3/46 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/7682 ,  H01L21/76825 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/535 ,  H01L27/228 ,  H01L29/02 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The deposition rate of a porous insulation film is increased, and the film strength of the porous insulation film is improved. Two or more organic siloxane raw materials each having a cyclic SiO structure as a main skeleton thereof, and having mutually different structures, are vaporized, and transported with a carrier gas to a reactor (chamber), and an oxidant gas including an oxygen atom is added thereto. Thus, a porous insulation film is formed by a plasma CVD (Chemical Vapor Deposition) method or a plasma polymerization method in the reactor (chamber). In the step, the ratio of the flow rate of the added oxidant gas to the flow rate of the carrier gas is more than 0 and 0.08 or less.

Abstract translation: 多孔绝缘膜的沉积速率提高，多孔绝缘膜的膜强度提高。 两种以上的具有环状SiO结构作为主要骨架并且具有相互不同结构的有机硅氧烷原料被蒸发并用载气输送到反应器（室），并且包含氧原子的氧化剂气体是 加入。 因此，在反应器（室）中通过等离子体CVD（化学气相沉积）法或等离子体聚合法形成多孔绝缘膜。 在该步骤中，添加的氧化剂气体的流量与载气的流量的比率大于0和0.08以下。

公开(公告)号：US09230865B2

公开(公告)日：2016-01-05

申请号：US14710111

申请日：2015-05-12

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi Sunamura ,  Kishou Kaneko ,  Naoya Furutake ,  Shinobu Saitou ,  Yoshihiro Hayashi

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L21/00 ,  H01L21/8254 ,  H01L29/786

CPC classification number: H01L21/823807 ,  H01L21/8238 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/8254 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/7869

Abstract: A semiconductor device is provided which includes an N-type semiconductor layer and a P-type semiconductor layer coexisting in the same wiring layer without influences on the properties of a semiconductor layer. The semiconductor device includes a first wiring layer with a first wiring, a second wiring layer with a second wiring, and first and second transistors provided in the first and second wiring layers. The first transistor includes a first gate electrode, a first gate insulating film, a first oxide semiconductor layer, a first hard mask layer, and first insulating sidewall films covering the sides of the first oxide semiconductor layer. The second transistor includes a second gate electrode, a second gate insulating film, a second oxide semiconductor layer, and a second hard mask layer.