公开(公告)号：US08574976B2

公开(公告)日：2013-11-05

申请号：US12904235

申请日：2010-10-14

Applicant: Shunpei Yamazaki ,  Naoto Kusumoto ,  Hideto Ohnuma ,  Koichiro Tanaka

Inventor： Shunpei Yamazaki ,  Naoto Kusumoto ,  Hideto Ohnuma ,  Koichiro Tanaka

IPC: H01L21/00

CPC classification number: H01L27/127 ,  G02F1/13454 ,  H01L27/1203 ,  H01L27/1214 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78696

Abstract: A TFT having a high threshold voltage is connected to the source electrode of each TFT that constitutes a CMOS circuit. In another aspect, pixel thin-film transistors are constructed such that a thin-film transistor more distant from a gate line drive circuit has a lower threshold voltage. In a further aspect, a control film that is removable in a later step is formed on the surface of the channel forming region of a TFT, and doping is performed from above the control film.

公开(公告)号：US08471262B2

公开(公告)日：2013-06-25

申请号：US13238754

申请日：2011-09-21

Applicant: Shunpei Yamazaki ,  Satoshi Murakami ,  Jun Koyama ,  Yukio Tanaka ,  Hidehito Kitakado ,  Hideto Ohnuma

Inventor： Shunpei Yamazaki ,  Satoshi Murakami ,  Jun Koyama ,  Yukio Tanaka ,  Hidehito Kitakado ,  Hideto Ohnuma

IPC: H01L27/14

CPC classification number: G02F1/1368 ,  G02F1/133345 ,  G02F1/13454 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2201/123 ,  G02F2202/104 ,  H01L27/12 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/3248 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3272 ,  H01L27/3276 ,  H01L29/458 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78675 ,  H01L2029/7863 ,  H01L2227/323

Abstract: This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant to hot carrier injection is achieved. LDD regions 717, 718, 719 and 720 not overlapping with a gate wiring are arranged in an n-channel TFT 804 forming a pixel unit. As a result, a TFT structure having a small OFF current value is achieved. In this instance, an element belonging to the Group 15 of the Periodic Table exists in a higher concentration in the LDD region 707 than in the LDD regions 717, 718, 719 and 720.

公开(公告)号：US08470648B2

公开(公告)日：2013-06-25

申请号：US12899993

申请日：2010-10-07

Applicant: Shunpei Yamazaki ,  Hideto Ohnuma ,  Tetsuya Kakehata

Inventor： Shunpei Yamazaki ,  Hideto Ohnuma ,  Tetsuya Kakehata

IPC: H01L21/762

CPC classification number: H01L27/1266 ,  H01L21/31662 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1214 ,  H01L27/1229 ,  H01L29/66772 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2224/80001

Abstract: A semiconductor device including a plurality of field-effect transistors which are stacked with a planarization layer interposed therebetween over a substrate having an insulating surface, in which semiconductor layers in the plurality of field-effect transistors are separated from semiconductor substrates, and the semiconductor layers are bonded to an insulating layer formed over the substrate having an insulating surface or an insulating layer formed over the planarization layer.

Abstract translation: 一种半导体器件，包括多个场效应晶体管，所述多个场效应晶体管在其间具有绝缘表面的衬底上层叠有平坦化层，所述多个场效应晶体管中的半导体层与半导体衬底分离，并且所述半导体层 被结合到形成在具有形成在平坦化层上的绝缘表面或绝缘层的衬底上的绝缘层。

公开(公告)号：US08324032B2

公开(公告)日：2012-12-04

申请号：US13152492

申请日：2011-06-03

Applicant: Hideto Ohnuma ,  Ichiro Uehara

Inventor： Hideto Ohnuma ,  Ichiro Uehara

IPC: H01L21/84

CPC classification number: H01L27/1288 ,  H01L21/28114 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/1214 ,  H01L29/42384 ,  H01L29/66598 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L2029/7863 ,  Y10S438/949

Abstract: Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order to perform formation of LDD structures and GOLD structures only by processes such as dry etching, the transistor structures all have the same structure, and it is difficult to form LDD structures, GOLD structures, and single drain structures separately for different circuits. By applying a photolithography process for forming gate electrodes to photomasks or reticles, in which supplemental patterns having a function of reducing, the intensity of light and composed of diffraction grating patterns or translucent films, are established, GOLD structure, LDD structure, and single drain structure transistors can be easily manufactured for different circuits through dry etching and ion injection process steps.

Abstract translation: 通常以半导体器件中的LDD结构和GOLD结构的形式，以栅电极作为掩模进行自对准，但是栅电极具有两层结构的情况很多，成膜工艺和蚀刻工艺变得复杂。 此外，为了仅通过诸如干蚀刻的工艺来形成LDD结构和GOLD结构，晶体管结构都具有相同的结构，并且难以分别形成用于不同电路的LDD结构，GOLD结构和单个漏极结构 。 通过对光栅掩模或掩模版形成栅极电极的光刻工艺，建立了具有降低光的强度并由衍射光栅图案或半透明膜构成的功能的补充图案，GOLD结构，LDD结构和单漏极 通过干蚀刻和离子注入工艺步骤可以容易地为不同的电路制造结构晶体管。

公开(公告)号：US08273613B2

公开(公告)日：2012-09-25

申请号：US12621537

申请日：2009-11-19

Applicant: Hongyong Zhang ,  Yasuhiko Takemura ,  Toshimitsu Konuma ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi

Inventor： Hongyong Zhang ,  Yasuhiko Takemura ,  Toshimitsu Konuma ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi

IPC: H01L21/84

CPC classification number: H01L27/127 ,  H01L27/1214 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627

Abstract: There is provided a method by which lightly doped drain (LDD) regions can be formed easily and at good yields in source/drain regions in thin film transistors possessing gate electrodes covered with an oxide covering. A lightly doped drain (LDD) region is formed by introducing an impurity into an island-shaped silicon film in a self-aligning manner, with a gate electrode serving as a mask. First, low-concentration impurity regions are formed in the island-shaped silicon film by using rotation-tilt ion implantation to effect ion doping from an oblique direction relative to the substrate. Low-concentration impurity regions are also formed below the gate electrode at this time. After that, an impurity at a high concentration is introduced normally to the substrate, so forming high-concentration impurity regions. In the above process, a low-concentration impurity region remains below the gate electrode and constitutes a lightly doped drain region.

Abstract translation: 提供了一种方法，通过该方法可以容易地形成轻掺杂漏极（LDD）区域，并且在具有覆盖有氧化物覆盖层的栅电极的薄膜晶体管中的源/漏区域中以良好的产率形成。 通过以栅极电极作为掩模，以自对准的方式将杂质引入岛状硅膜中形成轻掺杂漏极（LDD）区域。 首先，通过使用旋转 - 倾斜离子注入在岛状硅膜中形成低浓度杂质区，以相对于衬底从倾斜方向进行离子掺杂。 此时也在栅电极下方形成低浓度杂质区。 之后，将高浓度的杂质通常引入衬底，从而形成高浓度杂质区域。 在上述过程中，低浓度杂质区域保留在栅电极下方并构成轻掺杂漏区。

公开(公告)号：US20120193435A1

公开(公告)日：2012-08-02

申请号：US13361988

申请日：2012-01-31

Applicant: Kazuya HANAOKA ,  Hideto Ohnuma ,  Teruyuki Fujii

Inventor： Kazuya HANAOKA ,  Hideto Ohnuma ,  Teruyuki Fujii

IPC: G06K19/077

CPC classification number: H01Q1/2208 ,  H01Q9/0407 ,  H01Q23/00

Abstract: An object of the present invention is to prevent electrical characteristics of circuit elements from being adversely affected by copper diffusion in a semiconductor device having an integrated circuit and an antenna formed over one substrate, which uses copper plating for the antenna. Another object is to prevent a defect of a semiconductor device due to poor connection between an antenna and an integrated circuit in a semiconductor device having the integrated circuit and the antenna formed over one substrate. In a semiconductor device having an integrated circuit 100 and an antenna 101 formed over one substrate 102, when a copper plating layer 108 is used for a conductor of the antenna 101, it is possible to decrease an adverse effect on electrical characteristics of circuit elements due to copper diffusion because a base layer 107 of the antenna 101 uses a nitride film of a predetermined metal.

Abstract translation: 本发明的目的是为了防止在具有集成电路的半导体器件中的电路元件的电气特性受到不利影响，并且在一个衬底上形成天线，该衬底使用用于天线的铜电镀。 另一个目的是防止在具有集成电路的半导体器件中的天线与集成电路之间的不良连接导致半导体器件的缺陷，并且形成在一个衬底上的天线。 在具有集成电路100和在一个基板102上形成的天线101的半导体器件中，当将铜镀层108用于天线101的导体时，可以减少对电路元件的电特性的不利影响， 由于天线101的基极层107使用预定金属的氮化物膜而导致铜扩散。

公开(公告)号：US08222117B2

公开(公告)日：2012-07-17

申请号：US12076794

申请日：2008-03-24

Applicant: Shunpei Yamazaki ,  Hideto Ohnuma

Inventor： Shunpei Yamazaki ,  Hideto Ohnuma

IPC: H01L21/30

CPC classification number: H01L21/76254 ,  G06K19/07749 ,  G06K19/0775 ,  G06K19/07786 ,  H01L21/84 ,  H01L24/83 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/83851 ,  H01L2924/00011 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2224/29075 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An SOI substrate and a manufacturing method of the SOI substrate, by which enlargement of the substrate is possible and its productivity can be increased, are provided. A step (A) of cutting a single crystal silicon substrate to form a single crystal silicon substrate which is n (n is an optional positive integer, n≧1) times as large as a size of one shot of an exposure apparatus; a step (B) of forming an insulating layer on one surface of the single crystal silicon substrate, and forming an embrittlement layer in the single crystal substrate; and a step (C) of bonding a substrate having an insulating surface and the single crystal silicon substrate with the insulating layer therebetween, and conducting heat treatment to separate the single crystal silicon substrate along the embrittlement layer, and forming a single crystal silicon thin film on the substrate having an insulating surface are conducted.

Abstract translation: 提供SOI衬底和SOI衬底的制造方法，通过其可以扩大衬底并提高其生产率。 一种切割单晶硅衬底以形成单一曝光设备的一个大小的n（n是任选的正整数，n≥1）倍的单晶硅衬底的步骤（A）; 在单晶硅衬底的一个表面上形成绝缘层并在单晶衬底中形成脆化层的步骤（B）; 以及使具有绝缘面的基板与单晶硅基板之间具有绝缘层的步骤（C），并进行热处理以沿着脆化层分离单晶硅基板，并且形成单晶硅薄膜 在具有绝缘表面的基板上进行。

公开(公告)号：US08143118B2

公开(公告)日：2012-03-27

申请号：US12073618

申请日：2008-03-07

Applicant: Hideto Ohnuma ,  Atsuo Isobe ,  Hiromichi Godo

Inventor： Hideto Ohnuma ,  Atsuo Isobe ,  Hiromichi Godo

IPC: H01L21/84

CPC classification number: H01L29/78696 ,  H01L21/0237 ,  H01L21/02675 ,  H01L21/02691 ,  H01L27/1281

Abstract: A semiconductor device having a highly responsive thin film transistor (TFT) with low subthreshold swing and suppressed decrease in the on-state current and a manufacturing method thereof are demonstrated. The TFT of the present invention is characterized by its semiconductor layer where the thickness of the source region or the drain region is larger than that of the channel formation region. Manufacture of the TFT is readily achieved by the formation of an amorphous semiconductor layer on a projection portion and a depression portion, which is followed by subjecting the melting process of the semiconductor layer, resulting in the formation of a crystalline semiconductor layer having different thicknesses. Selective addition of impurity to the thick portion of the semiconductor layer provides a semiconductor layer in which the channel formation region is thinner than the source or drain region.

Abstract translation: 示出了具有低亚阈值摆动和抑制导通电流下降的高响应性薄膜晶体管（TFT）的半导体器件及其制造方法。 本发明的TFT的特征在于其源极区域或漏极区域的厚度大于沟道形成区域的厚度的半导体层。 通过在突起部分和凹陷部分上形成非晶半导体层来容易地实现TFT的制造，随后对半导体层进行熔化处理，形成具有不同厚度的晶体半导体层。 选择性地向半导体层的厚部分添加杂质提供了沟道形成区域比源区或漏区更薄的半导体层。

公开(公告)号：US08110478B2

公开(公告)日：2012-02-07

申请号：US12253301

申请日：2008-10-17

Applicant: Shunpei Yamazaki ,  Hideto Ohnuma ,  Jun Koyama

Inventor： Shunpei Yamazaki ,  Hideto Ohnuma ,  Jun Koyama

IPC: H01L21/76

CPC classification number: H01L27/1266 ,  C03C17/3435 ,  C03C17/3482 ,  C03C2218/32 ,  H01L21/76254 ,  H01L27/1214 ,  H01L29/66772 ,  Y10S438/938 ,  Y10S438/961

Abstract: If the size of a single crystal silicon layer attached is not appropriate, even when a large glass substrate is used, the number of panels to be obtained cannot be maximized. Therefore, in the present invention, a substantially quadrangular single crystal semiconductor substrate is formed from a substantially circular single crystal semiconductor wafer, and a damaged layer is formed by irradiation with an ion beam into the single crystal semiconductor substrate. A plurality of the single crystal semiconductor substrates are arranged so as to be separated from each other over one surface of a supporting substrate. By thermal treatment, a crack is generated in the damaged layer and the single crystal semiconductor substrate is separated while a single semiconductor layer is left over the supporting substrate. After that, one or a plurality of display panels is manufactured from the single crystal semiconductor layer bonded to the supporting substrate.

Abstract translation: 如果附着的单晶硅层的尺寸不合适，即使使用大的玻璃基板，也不能使要获得的面板的数量最大化。 因此，在本发明中，从大致圆形的单晶半导体晶片形成大致四边形的单晶半导体基板，通过将离子束照射到单晶半导体基板中形成损伤层。 多个单晶半导体基板被布置成在支撑基板的一个表面上彼此分离。 通过热处理，在损伤层中产生裂纹，并且单个半导体衬底被分离，而单个半导体层留在支撑衬底上。 之后，从结合到支撑基板的单晶半导体层制造一个或多个显示面板。

公开(公告)号：US07947538B2

公开(公告)日：2011-05-24

申请号：US12534176

申请日：2009-08-03

Applicant: Hideto Ohnuma ,  Masaharu Nagai ,  Mitsuaki Osame ,  Masayuki Sakakura ,  Shigeki Komori ,  Shunpei Yamazaki

Inventor： Hideto Ohnuma ,  Masaharu Nagai ,  Mitsuaki Osame ,  Masayuki Sakakura ,  Shigeki Komori ,  Shunpei Yamazaki

IPC: H01L21/00

CPC classification number: H01L27/124 ,  H01L27/1214 ,  H01L27/1251 ,  H01L27/1288 ,  H01L27/14623 ,  H01L27/3244 ,  H01L29/78645

Abstract: It is an object of the present invention to form a plurality of elements in a limited area to reduce the area occupied by the elements for integration so that further higher resolution (increase in number of pixels), reduction of each display pixel pitch with miniaturization, and integration of a driver circuit that drives a pixel portion can be advanced in semiconductor devices such as liquid crystal display devices and light-emitting devices that has EL elements. A photomask or a reticle provided with an assist pattern that is composed of a diffraction grating pattern or a semi-transparent film and has a function of reducing a light intensity is applied to a photolithography process for forming a gate electrode to form a complicated gate electrode. In addition, a top-gate TFT that has the multi-gate structure described above and a top gate TFT that has a single-gate structure can be formed on the same substrate just by changing the mask without increasing the number of processes.

Abstract translation: 本发明的目的是在有限的区域中形成多个元件，以减少用于积分的元件所占据的面积，从而进一步提高分辨率（增加像素数），减小每个显示像素间距，同时小型化， 并且驱动像素部分的驱动电路的集成可以在具有EL元件的液晶显示装置和发光装置等半导体装置中进行。 将具有由衍射光栅图案或半透明膜构成的辅助图案的光掩模或掩模版施加到用于形成栅电极的光刻工艺以形成复杂的栅电极 。 此外，只要通过改变掩模而不增加处理次数，就可以在同一基板上形成具有上述多栅结构的顶栅TFT和具有单栅结构的顶栅TFT。