公开(公告)号：US12298909B2

公开(公告)日：2025-05-13

申请号：US18231730

申请日：2023-08-08

Applicant: Sandisk Technologies, Inc.

Inventor： Chao Sun ,  Qingbo Wang ,  Minghai Qin ,  Jaco Hofmann ,  Anand Kulkarni ,  Dejan Vucinic ,  Zvonimir Bandic

IPC: G06F12/0862 ,  G06N20/00

Abstract: A memory device includes a first memory and a second memory that caches data stored in the first memory. At least one controller of the memory device receives page fault information from a host. The page fault information results from a request for data by the host that is stored in the first memory but is not cached in the second memory when requested by the host. The memory device uses the received page fault information for one or more inputs into a prefetch model trained by Machine Learning (ML) to generate at least one inference. Based at least in part on the at least one inference, prefetch data is cached in the second memory. In one aspect, the page fault information is used to train the prefetch model. In another aspect, the page fault information includes at least one virtual address used by the host for the requested data.

公开(公告)号：US20250147097A1

公开(公告)日：2025-05-08

申请号：US18504413

申请日：2023-11-08

Applicant: Sandisk Technologies, Inc.

Inventor： John Patrick Burke

IPC: G01R31/28

Abstract: A PCB test coupon is used to determine a back drilling depth to remove a stub from a PCB. A number of conductors are placed at various layers within the PCB test coupon. Vias connect each end of a conductor to a surface layer of the PCB test coupon and form test points on the surface layer of the PCB test coupon. To determine a depth of each conductor, an inductive test probe is placed on the surface layer of the PCB test coupon. The inductive test probe generates and emits an alternating magnetic field which acts on the conductors and causes a crosstalk voltage to occur across the test points. The voltage across the test points is proportional to the distance of the conductors in each layer of the PCB test coupon.

公开(公告)号：US12289887B2

公开(公告)日：2025-04-29

申请号：US17664542

申请日：2022-05-23

Applicant: Sandisk Technologies, Inc.

Inventor： Peter Rabkin ,  Masaaki Higashitani

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A memory device includes an alternating stack of insulating layers and control gate layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure containing a memory film and a vertical semiconductor channel located within the memory opening. The memory film includes a resonant tunneling barrier stack, a barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the barrier layer. The barrier layer may be a dielectric blocking barrier layer.

公开(公告)号：US12277334B2

公开(公告)日：2025-04-15

申请号：US18448905

申请日：2023-08-11

Applicant: Sandisk Technologies, Inc.

Inventor： Nitin Jain ,  Ronak Jain ,  Matthew Klapman ,  Ramanathan Muthiah ,  Taninder Singh Sijher

IPC: G06F3/06

Abstract: A data storage device includes storage media and control circuitry and is configured to enable the creation of partitions with different performance levels. The storage media includes a first set and a second set of memory blocks having different performance levels. The control circuitry is configured to: in response to a request from a host system, provide performance data from the first set of memory blocks and the second set of memory blocks to the host system. The control circuitry is further configured to: receive partition settings from the host system, the partition settings creating a first partition including at least part of the first set of memory blocks and a second partition including at least part of the second set of memory blocks, wherein the first partition has a better performance level than the second partition; and save the partition settings to the storage media.

公开(公告)号：US20250054818A1

公开(公告)日：2025-02-13

申请号：US18930628

申请日：2024-10-29

Applicant: Sandisk Technologies, Inc.

Inventor： Akira Ogawa ,  Takashi Murai

IPC: H01L21/66 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: An apparatus includes a semiconductor wafer including a first die and a second die, each including, a selector circuit including a first input terminal coupled to a first die bond pad, a second input terminal, and an output terminal, the selector circuit configured to selectively couple the first input terminal and the second input terminal to the output terminal, a conductor selectively configured to couple the second input terminal to either a first power supply or a second power supply, and an address determined based on a signal value at the output terminal of the selector circuit.

公开(公告)号：US20250004660A1

公开(公告)日：2025-01-02

申请号：US18230145

申请日：2023-08-03

Applicant: Sandisk Technologies, Inc.

Inventor： Daniel J. Linnen ,  Ramanathan Muthiah ,  Preston Thomson ,  Kirubakaran Periyannan ,  Niles Nian Yang ,  Inez Hua ,  Judah Gamliel Hahn

IPC: G06F3/06

Abstract: A process for reliably erasing data from a solid-state drive (SSD) includes first, prior to user data being stored on the drive, generating a restore image of information stored on the drive which characterizes a restore state of the drive, such as a factory image. Then, imparting energy to the drive to promote electrons representing bits in corresponding memory cells to exit the cells, such as imparting thermal energy or high-energy electromagnetic radiation to the drive. Also, generating a set of quantitative data for verifying erasure of the data for presentation to the user helps ensure trust in the data wipe process. The drive may also be electrically erased prior to imparting energy to the SSD, to provide another level of confidence in the data wipe process. The restore image may then be loaded to the necessary locations on the wiped drive to restore drive functionality.

公开(公告)号：US20240395328A1

公开(公告)日：2024-11-28

申请号：US18790609

申请日：2024-07-31

Applicant: Sandisk Technologies, Inc.

Inventor： Abhijith Prakash ,  Anubhav Khandelwal

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/32 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: The nonvolatile memory includes a plurality of nonvolatile memory cells configured to store multiple data states; a word line connected to a control gate of at least one of the plurality of non-volatile memory cells; a control gate line to supply a control gate signal; a word line switch connected between the word line and the control gate line to control the potential applied to the word line from the control gate line; and a memory controller circuit. The memory controller circuit is configured to control a word line potential on the word line and a control gate potential on the control gate line and to control a state of the control gate. The memory controller circuit, when the nonvolatile memory transitions to a not-on state, is further configured to turn off the word line switch and to charge the control gate line to a charged potential.

公开(公告)号：US12124704B2

公开(公告)日：2024-10-22

申请号：US18356693

申请日：2023-07-21

Applicant: Western Digital Technologies, Inc.

Inventor： Asaf Gueta ,  Arie Star ,  Omer Fainzilber ,  Eran Sharon

IPC: G06F3/06

CPC classification number: G06F3/0614 ,  G06F3/064 ,  G06F3/0679

Abstract: A storage device includes a memory die and a controller. The controller identifies a dirty block that was subject to an interrupted I/O operation and performs a coarse inspection of the dirty block. Each iteration of the coarse inspection includes: requesting first bytes of a current page of the dirty block; receiving contents of the first bytes from the at least one memory die; and evaluating a state of the current page based on the contents of the first bytes. The controller also determines an initial last good page based on the coarse inspection and performs a fine inspection of at least one page based on a second number of bytes greater than the first number of bytes. The fine inspection validates the initial last good page and identifies the initial last good page as an actual last good page of the dirty block.

公开(公告)号：US12118242B2

公开(公告)日：2024-10-15

申请号：US17657456

申请日：2022-03-31

Applicant: Western Digital Technologies, Inc.

Inventor： Judah Gamliel Hahn ,  Shay Benisty ,  Ariel Navon

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0679

Abstract: The present disclosure generally relates to host memory buffer (HMB) cache management in DRAM-less SSDs. HMB is transient memory and may not always be available. For example, when the link between the data storage device and the host device is not active, the data storage device can't access the HMB. Placing an HMB log in the HMB controller that is disposed in the data storage device provides access to data that would otherwise be inaccessible in the HMB. The HMB log contains any deltas that have occurred since either the last copying to an HMB cache in the memory device or any delta that have occurred since the link became inactive. The HMB cache mirrors the HMB. In so doing, the data of the HMB is available to the data storage device not only when the link is active, but also when the link is not active.

公开(公告)号：US12114435B2

公开(公告)日：2024-10-08

申请号：US17744291

申请日：2022-05-13

Applicant: Sandisk Technologies, Inc.

Inventor： Virgil Zhu ,  Vincent Jiang ,  Paul Qu ,  Shixing Zhu ,  Yuanheng Zhang ,  Enoch He ,  Yonglong Liu ,  Lian Chen ,  Guangqiang Li ,  Jingyun Chen

IPC: B23K1/00 ,  B23K3/00 ,  B23K37/04 ,  H05K3/34 ,  B23K101/42

CPC classification number: H05K3/3494 ,  B23K1/0016 ,  B23K37/04 ,  H05K3/341 ,  H05K3/3457 ,  B23K2101/42

Abstract: A method of soldering one or more components to a substrate includes providing a substrate and applying an amount of solder material to the top planar surface of the substrate. One or more electrical components are mounted to the solder material in a predetermined position and orientation. A carrier is provided having one or more magnets embedded therein. The substrate is positioned above the carrier such that each of the one or more magnets is positioned directly below a corresponding electrical component. A carrier cover is positioned above the substrate and the electrical components. The solder material is heated to a predetermined temperature for a predetermined amount of time during which each of the magnets exerts a magnetic force on a corresponding electrical component to maintain its orientation relative to the substrate. The magnets reduce the occurrence of tombstoning of the electrical components during heating of the solder material.