Routing of a gate signal for controlling a discrete power switching device (such as in an inverter for an electric vehicle drive) is configured to compensate for the common source inductance inherent in the switching device as a result of its integrated circuit packaging. The power device has a gate signal path via a gate pin and a power signal path via first and second power pins, wherein the gate signal path and the power signal path have a first mutual inductance. A circuit board apparatus provides a gate wiring loop juxtaposed with the power signal path, wherein the gate wiring loop and the power signal path have a second mutual inductance substantially canceling the first mutual inductance. The resulting reduction in common source inductance avoids the reductions in switching speed and the increased switching losses otherwise introduced by the common source inductance.