Invention Grant
- Patent Title: Dynamic current limit circuit
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Application No.: US15255903Application Date: 2016-09-02
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Publication No.: US09991784B2Publication Date: 2018-06-05
- Inventor: Mark Childs , Martin Faerber , Jens Masuch , Giulio de Vita
- Applicant: Dialog Semiconductor (UK) Limited
- Applicant Address: GB London
- Assignee: Dialog Semiconductor (UK) Limited
- Current Assignee: Dialog Semiconductor (UK) Limited
- Current Assignee Address: GB London
- Agency: Saile Ackerman LLC
- Agent Stephen B. Ackerman
- Main IPC: H03M1/00
- IPC: H03M1/00 ; H02M1/32 ; H02M3/158 ; H02M1/00

Abstract:
A system is disclosed which provides a dynamic current limit circuit that accurately defines both the lower and the upper limits for the current limit. The circuit ensures both the lower and upper current limits are well-controlled. The lower current limit is matched to the normal pulse-frequency modulation (PFM) limit, and the upper current limit is matched to the pulse-width modulation (PWM) limit. This implementation has several key benefits, including making the peak current limit accurate in both sync and dynamic sleep modes. If the scheme is carefully designed, the dynamic sleep current limit gives the best load transient response.
Public/Granted literature
- US20180069468A1 Dynamic Current Limit Circuit Public/Granted day:2018-03-08
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