Invention Grant
- Patent Title: Method for fabricating a fin field effect transistor and a shallow trench isolation
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Application No.: US15054113Application Date: 2016-02-25
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Publication No.: US09991154B2Publication Date: 2018-06-05
- Inventor: Wei Ken Lin , Jia-Ming Lin , Hsien-Che Teng , Yung-Chou Shih , Kun-Dian She , Lichia Yang , Yun-Wen Chu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: H01L21/76
- IPC: H01L21/76 ; H01L21/762 ; H01L21/02 ; H01L29/78 ; H01L29/66
Abstract:
A method for fabricating a shallow trench isolation (STI) structure comprises the following steps. A silane-base precursor having a volumetric flowrate of 500 to 750 sccm and a nitrogen-base precursor having a volumetric flowrate of 300 to 600 sccm are introduced and mixed under a first pressure ranging from 0.5 to 1.5 torr at a first temperature ranging from 30 to 105 centigrade to deposit a flowable dielectric layer in a trench of a substrate. Then, ozone gas and oxygen gas are introduced and mixed under a second pressure ranging from 300 to 650 torr at a second temperature ranging from 50 to 250 centigrade to treat the flowable dielectric layer, wherein a volumetric flowrate ratio of ozone gas and oxygen gas ranges from 1:1 to 3:1. A method for fabricating a FinFET is provided.
Public/Granted literature
- US20170250106A1 METHOD FOR FABRICATING A FIN FIELD EFFECT TRANSISTOR AND A SHALLOW TRENCH ISOLATION Public/Granted day:2017-08-31
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