Invention Grant
- Patent Title: Bounding volume hierarchy generation using a heterogeneous architecture
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Application No.: US14574992Application Date: 2014-12-18
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Publication No.: US09990758B2Publication Date: 2018-06-05
- Inventor: Per Ganestam , Tomas Akenine-Moller , Carl J. Munkberg
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop Pruner & Hu, P.C.
- Main IPC: G06T15/00
- IPC: G06T15/00 ; G06T17/00

Abstract:
A system rapidly builds bounding volume hierarchies for ray tracing using both the CPU cores and an integrated graphics processor. The hierarchy is built directly into shared memory (between the CPU and GPU). The method starts by sorting the triangles along a space-filling curve, and then quickly sets up a number of mini-trees with a small number of triangles in them, which includes computing the bounding boxes of the mini-trees. This makes it possible to build the mini-trees using a surface-area heuristic in parallel on the graphics processor, while at the same time, the trees above the mini-trees are built in a top-down fashion using the CPU cores.
Public/Granted literature
- US20150279092A1 Bounding Volume Hierarchy Generation Using a Heterogeneous Architecture Public/Granted day:2015-10-01
Information query
IPC分类:
G | 物理 |
G06 | 计算;推算或计数 |
G06T | 一般的图像数据处理或产生 |
G06T15/00 | 3D〔三维〕图像的加工 |