Methods and systems for checking a wafer-level design for compliance with a rule include identifying nets that cross chip boundaries for each of a plurality of chip layouts. Net properties are determined for each of the identified nets. Interconnected identified nets are combined into one or more virtual ensembles having properties defined by a sum of the properties of the respective interconnected nets. Each virtual ensemble is evaluated for compliance with a design rule. The chip layouts related to virtual ensembles that do not comply with the design rule are modified to bring non-compliant virtual ensembles into compliance.