Invention Grant
- Patent Title: Interlayer filler composition for three-dimensional integrated circuit
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Application No.: US13865318Application Date: 2013-04-18
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Publication No.: US09960092B2Publication Date: 2018-05-01
- Inventor: Makoto Ikemoto , Yasuhiro Kawase , Tomohide Murase , Makoto Takahashi , Takayoshi Hirai , Iho Kamimura
- Applicant: MITSUBISHI CHEMICAL CORPORATION
- Applicant Address: JP Chiyoda-ku
- Assignee: Mitsubishi Chemical Corporation
- Current Assignee: Mitsubishi Chemical Corporation
- Current Assignee Address: JP Chiyoda-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2010-274544 20100912; JP2010-233799 20101018; JP2010-268412 20101201; JP2010-268413 20101201
- Main IPC: H01L23/18
- IPC: H01L23/18 ; H01L23/00 ; C09D163/00 ; C08L63/00

Abstract:
To provide an interlayer filler composition which, in 3D lamination of semiconductor device chips, forms a highly thermally conductive filling interlayer simultaneously with the bonding of solder bumps or the like and lands between semiconductor device chips, a coating fluid and a process for producing a three-dimensional integrated circuit.An interlayer filler composition for a three-dimensional integrated circuit, which comprises a resin (A) having a melt viscosity at 120° C. of at most 100 Pa·s and a flux (B), the content of the flux (B) being at least 0.1 part by weight and at most 10 parts by weight per 100 parts by weight of the resin (A).
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