Invention Grant
- Patent Title: Enhanced cyclical redundancy check circuit based on galois-field arithmetic
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Application No.: US14980201Application Date: 2015-12-28
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Publication No.: US09935653B2Publication Date: 2018-04-03
- Inventor: Sivakumar Radhakrishnan , Sin S. Tan , Kenneth C. Haren , Mark A. Schmisseur
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alpine Technology Law Group LLC
- Main IPC: H03M13/07
- IPC: H03M13/07 ; H03M13/09

Abstract:
Methods and apparatus related to enhanced Cyclical Redundancy Check (CRC) circuit based on Galois-Field arithmetic are described. In one embodiment, a plurality of exclusive OR logic include first exclusive OR logic and second exclusive OR logic. First Galois Field multiplier logic multiplies a first output from the first exclusive OR logic and a first portion of a plurality of portions of the input data. Second Galois Field multiplier logic multiplies a second output from the second exclusive OR logic and a second portion of the plurality of portions of the input data. Other embodiments are also disclosed and claimed.
Public/Granted literature
- US20170187389A1 ENHANCED CYCLICAL REDUNDANCY CHECK CIRCUIT BASED ON GALOIS-FIELD ARITHMETIC Public/Granted day:2017-06-29
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