Invention Grant
- Patent Title: Method for making semiconductor device with filled gate line end recesses
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Application No.: US15472556Application Date: 2017-03-29
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Publication No.: US09935179B2Publication Date: 2018-04-03
- Inventor: Xiuyu Cai , Qing Liu , Kejia Wang , Ruilong Xie , Chun-Chen Yeh
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES, Inc. , STMICROELECTRONICS, INC.
- Applicant Address: US NY Armonk KY Grand Cayman US TX Coppell
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION,GLOBALFOUNDRIES INC.,STMICROELECTRONICS, INC.
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION,GLOBALFOUNDRIES INC.,STMICROELECTRONICS, INC.
- Current Assignee Address: US NY Armonk KY Grand Cayman US TX Coppell
- Agency: Cantor Colburn LLP
- Agent Steven Meyers
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L29/66 ; H01L29/06 ; H01L27/088 ; H01L21/8234

Abstract:
A method for making a semiconductor device may include forming first and second spaced apart semiconductor active regions with an insulating region therebetween, forming at least one sacrificial gate line extending between the first and second spaced apart semiconductor active regions and over the insulating region, and forming sidewall spacers on opposing sides of the at least one sacrificial gate line. The method may further include removing portions of the at least one sacrificial gate line within the sidewall spacers and above the insulating region defining at least one gate line end recess, filling the at least one gate line end recess with a dielectric material, and forming respective replacement gates in place of portions of the at least one sacrificial gate line above the first and second spaced apart semiconductor active regions.
Public/Granted literature
- US20170200812A1 METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH FILLED GATE LINE END RECESSES Public/Granted day:2017-07-13
Information query
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