Invention Grant
- Patent Title: Stacked semiconductor dies with selective capillary under fill
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Application No.: US14982196Application Date: 2015-12-29
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Publication No.: US09935082B2Publication Date: 2018-04-03
- Inventor: Mitsuhisa Watanabe
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L25/065 ; H01L23/31 ; H01L25/18 ; H01L25/00 ; H01L21/78

Abstract:
Stacked semiconductor dies are provided with selective capillary under fill to avoid wafer warpage during curing. In one embodiment, a method of manufacturing a semiconductor device includes forming at least three stacks of semiconductor dies over a substrate, the stacks spaced apart from one another by gaps. A first sealing material such as a capillary under fill material is deposited into a first subset of the gaps. A second sealing material such as a mold resin is deposited into a second subset of the gaps. The first and second sealing materials are cured, and the die stacks are then singulated.
Public/Granted literature
- US20170186729A1 STACKED SEMICONDUCTOR DIES WITH SELECTIVE CAPILLARY UNDER FILL Public/Granted day:2017-06-29
Information query
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