A memory circuit includes a plurality of memory cells and a tracking circuit. Each memory cell of the plurality of memory cells includes a cell transistor corresponding to a predetermined transistor configuration. The tracking circuit includes a first tracking bit line, a first tracking word line, a reference voltage node, and a first plurality of tracking cells. Each tracking cell of the first plurality of tracking cells includes a cell transistor corresponding to the predetermined transistor configuration. The cell transistors of the first plurality of tracking cells are electrically coupled in series between the first tracking bit line and the reference voltage node, and gate terminals of the cell transistors of the first plurality of tracking cells are electrically coupled with the first tracking word line.