Disclosed is a timing controller including: a receiving unit configured to receive image data; a buffer memory configured to temporarily store and output the received image data; a timing controller circuit configured to generate a transmission clock signal; and a transmitter configured to receive the transmission clock signal and a transmission data signal, wherein the transmission data signal includes the image data output by the buffer memory, wherein the transmitter is configured to transmit a transmission signal, wherein the transmission clock signal is embedded in the transmission data signal, and wherein the transmission clock signal has a magnitude different from the transmission data signal.