Invention Grant
- Patent Title: Strain compensation in transistors
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Application No.: US15447044Application Date: 2017-03-01
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Publication No.: US09911807B2Publication Date: 2018-03-06
- Inventor: Van H. Le , Benjamin Chu-Kung , Harold Hal W. Kennel , Willy Rachmady , Ravi Pillarisetty , Jack T. Kavalieros
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/02 ; H01L29/10 ; H01L29/08 ; H01L29/165 ; H01L29/78 ; H01L29/66 ; H01L29/15

Abstract:
Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.
Public/Granted literature
- US20170179228A1 STRAIN COMPENSATION IN TRANSISTORS Public/Granted day:2017-06-22
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