Invention Grant
- Patent Title: Stacked 3D semiconductor memory structure
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Application No.: US14976643Application Date: 2015-12-21
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Publication No.: US09911749B2Publication Date: 2018-03-06
- Inventor: Kei Sakamoto , Hiroshi Nakaki
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Minato-ku
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L27/115 ; H01L29/792 ; H01L21/28 ; H01L27/11582 ; H01L27/11573 ; H01L27/11563 ; H01L27/11565 ; H01L27/11575 ; H01L21/768 ; G11C16/04 ; H01L27/1157

Abstract:
According to one embodiment, a semiconductor memory device includes a substrate; a stacked body provided on the substrate and including a plurality of electrode layers; a semiconductor film; a charge storage film; an interconnect layer provided in the stacked body, the interconnect layer; a first contact portion; a first metal layer; and a second metal layer. The interconnect layer includes: a first portion including silicon; and a second portion provided on the first portion and including metal. The first metal layer is provided on the first contact portion. The second metal layer is provided on the first metal layer, and electrically connected to the interconnect layer.
Public/Granted literature
- US20170069651A1 SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2017-03-09
Information query
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