Invention Grant
- Patent Title: Self-aligned double spacer patterning process
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Application No.: US15470446Application Date: 2017-03-27
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Publication No.: US09911646B2Publication Date: 2018-03-06
- Inventor: Cheng-Hsiung Tsai , Yung-Hsu Wu , Tsung-Min Huang , Chung-Ju Lee , Tien-I Bao , Shau-Lin Shue
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/027 ; H01L21/033 ; H01L21/308 ; H01L21/311 ; H01L21/3213

Abstract:
Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a first hard mask layer over a semiconductor device layer, forming a set of mandrels over the first hard mask layer, and forming a first spacer layer over the set of mandrels and the first hard mask layer. The method further includes forming a second spacer layer over the first spacer layer, patterning the first spacer layer and the second spacer layer to form a mask pattern, and patterning the first hard mask layer using the mask pattern as a mask.
Public/Granted literature
- US20170200641A1 Self-Aligned Double Spacer Patterning Process Public/Granted day:2017-07-13
Information query
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