Invention Grant
- Patent Title: Method of fabricating a charge-trapping gate stack using a CMOS process flow
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Application No.: US15335209Application Date: 2016-10-26
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Publication No.: US09911613B2Publication Date: 2018-03-06
- Inventor: Krishnaswamy Ramkumar , Hui-Mei Shih
- Applicant: Cypress Semiconductor Corporation
- Applicant Address: US CA San Jose
- Assignee: Cypress Semiconductor Corporation
- Current Assignee: Cypress Semiconductor Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L21/02 ; H01L21/8234 ; H01L29/66 ; H01L29/792 ; H01L27/11568 ; H01L27/11573 ; H01L29/423 ; H01L29/51

Abstract:
A method of fabricating a memory device is described. Generally, the method includes forming a channel from a semiconducting material overlying a surface of a substrate, and forming dielectric stack on the channel. A first cap layer is formed over the dielectric stack, and a second cap layer including a nitride formed over the first cap layer. The first and second cap layers and the dielectric stack are then patterned to form a gate stack of a device. The second cap layer is removed and an oxidation process performed to form a blocking oxide over the dielectric stack, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.
Public/Granted literature
- US20170084465A1 METHOD OF FABRICATING A CHARGE-TRAPPING GATE STACK USING A CMOS PROCESS FLOW Public/Granted day:2017-03-23
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