A static random access memory (SRAM) chip includes a first and second conductor, a set of SRAM cells and a set of first and second tracking cells. The first conductor extends in a first direction, is coupled to a first supply voltage, and on a first metal layer. The second conductor extends in a second direction, is coupled to a second supply voltage, and on a second metal layer. A first cell of the set of first tracking cells includes a first tracking bit line conductor, first and second CMOS, and a first and second pass gate device. A first cell of the set of second tracking cells includes a third pass gate device, a third PU device, and a third PD device having a source configured to be electrically floating. A gate of the first PD device or the first PU device is electrically coupled to the first conductor.