A semiconductor chip test device may include: a guide plate having a seating groove formed at the bottom thereof; a substrate coupled to the bottom of the guide plate, and having an upper semiconductor chip mounted on the top surface thereof such that the upper semiconductor chip is positioned in the seating groove; an upper socket having upper pogo pins coupled to the bottom of the guide plate in a state where the upper pogo pins are in contact with bottom patterns of the substrate, and having lower pogo pins formed on the bottom surface thereof, wherein the upper pogo pins protrude upward, and the lower pogo pins protrude downward; and a lower socket having a lower semiconductor chip seated on the top surface thereof, the lower semiconductor chip being in contact with the lower pogo pins.