Invention Grant
- Patent Title: Semiconductor device and method of manufacturing the same
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Application No.: US14291095Application Date: 2014-05-30
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Publication No.: US09887211B2Publication Date: 2018-02-06
- Inventor: Yoshiki Yamamoto
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Tokyo
- Agency: Shapiro, Gabor and Rosenberger, PLLC
- Priority: JP2013-116265 20130531
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L21/84 ; H01L21/762 ; H01L27/11 ; H01L29/78

Abstract:
A semiconductor device using an SOI (Silicon On Insulator) substrate, capable of preventing malfunction of MISFETs (Metal Insulator Semiconductor Field Effect Transistor) and thus improving the reliability of the semiconductor device. Moreover, the parasitic resistance of the MISFETs is reduced, and the performance of the semiconductor device is improved. An epitaxial layer formed on an SOI layer above an SOI substrate is formed to have a large width so as to cover the ends of the upper surface of an isolation region adjacent to the SOI layer. By virtue of this, contact plugs of which formation positions are misaligned are prevented from being connected to a semiconductor substrate below the SOI layer. Moreover, by forming the epitaxial layer at a large width, the ends of the SOI layer therebelow are prevented from being silicided. As a result, increase in the parasitic resistance of MISFETs is prevented.
Public/Granted literature
- US20140353756A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2014-12-04
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