Invention Grant
- Patent Title: Method for manufacturing integrated circuit device
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Application No.: US14847582Application Date: 2015-09-08
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Publication No.: US09887098B2Publication Date: 2018-02-06
- Inventor: Katsunori Yahashi
- Applicant: TOSHIBA MEMORY CORPORATION
- Applicant Address: JP Minato-ku
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: H01L27/115
- IPC: H01L27/115 ; H01L21/8247 ; H01L21/3065 ; H01L21/311 ; H01L21/265 ; H01L27/11582 ; H01L27/11556 ; H01L27/11519 ; H01L27/11565 ; H01L29/66

Abstract:
According to one embodiment, a method is disclosed for manufacturing an integrated circuit device, the method can include forming a mask member on a first film, the mask member having a pattern, performing a first etching on the first film using the mask member as a mask to form a recessed section in the first film, forming a second film covering an inner side surface of the recessed section. The second film has a film thickness of preventing blockage of the recessed section, and performing a second etching on the second film and the first film via the recessed section. The performing of the second etching includes performing a third etching in a condition of an etching rate at a place smaller in curvature radius in the recessed section being lower than an etching rate at a place larger in curvature radius in the recessed section.
Public/Granted literature
- US20160379843A1 METHOD FOR MANUFACTURING INTEGRATED CIRCUIT DEVICE Public/Granted day:2016-12-29
Information query
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